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* [gcc r14-3073] RISC-V: Support neg VLS auto-vectorization
@ 2023-08-08 3:38 Lehua Ding
0 siblings, 0 replies; only message in thread
From: Lehua Ding @ 2023-08-08 3:38 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:8f4d2a4c984f168b8444672aa8f4a103e845dfbf
commit r14-3073-g8f4d2a4c984f168b8444672aa8f4a103e845dfbf
Author: Juzhe-Zhong <juzhe.zhong@rivai.ai>
Date: Tue Aug 8 11:06:24 2023 +0800
RISC-V: Support neg VLS auto-vectorization
#include "riscv_vector.h"
#define DEF_OP_V(PREFIX, NUM, TYPE, OP) \
void __attribute__ ((noinline, noclone)) \
PREFIX##_##TYPE##NUM (TYPE *restrict a, TYPE *restrict b) \
{ \
for (int i = 0; i < NUM; ++i) \
a[i] = OP b[i]; \
}
DEF_OP_V (neg, 16, int32_t, -)
After this patch:
neg_int32_t16:
vsetivli zero,16,e32,mf2,ta,ma
vle32.v v1,0(a1)
vneg.v v1,v1
vse32.v v1,0(a0)
ret
gcc/ChangeLog:
* config/riscv/autovec-vls.md (<optab><mode>2): Add VLS neg.
* config/riscv/vector.md: Ditto.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/vls/def.h: Ditto.
* gcc.target/riscv/rvv/autovec/vls/neg-1.c: New test.
Diff:
---
gcc/config/riscv/autovec-vls.md | 21 ++++++++
gcc/config/riscv/vector.md | 10 ++--
.../gcc.target/riscv/rvv/autovec/vls/def.h | 8 +++
.../gcc.target/riscv/rvv/autovec/vls/neg-1.c | 57 ++++++++++++++++++++++
4 files changed, 91 insertions(+), 5 deletions(-)
diff --git a/gcc/config/riscv/autovec-vls.md b/gcc/config/riscv/autovec-vls.md
index 4a9f8c8d0bc..1b1d940d779 100644
--- a/gcc/config/riscv/autovec-vls.md
+++ b/gcc/config/riscv/autovec-vls.md
@@ -181,3 +181,24 @@
riscv_vector::RVV_BINOP, operands);
DONE;
})
+
+;; -------------------------------------------------------------------------------
+;; ---- [INT] Unary operations
+;; -------------------------------------------------------------------------------
+;; Includes:
+;; - vneg.v/vnot.v
+;; -------------------------------------------------------------------------------
+
+(define_insn_and_split "<optab><mode>2"
+ [(set (match_operand:VLSI 0 "register_operand")
+ (any_int_unop:VLSI
+ (match_operand:VLSI 1 "register_operand")))]
+ "TARGET_VECTOR && can_create_pseudo_p ()"
+ "#"
+ "&& 1"
+ [(const_int 0)]
+{
+ insn_code icode = code_for_pred (<CODE>, <MODE>mode);
+ riscv_vector::emit_vlmax_insn (icode, riscv_vector::RVV_UNOP, operands);
+ DONE;
+})
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index 151b0e33185..e56a2bf4bed 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -3386,8 +3386,8 @@
;; -------------------------------------------------------------------------------
(define_insn "@pred_<optab><mode>"
- [(set (match_operand:VI 0 "register_operand" "=vd,vd, vr, vr")
- (if_then_else:VI
+ [(set (match_operand:V_VLSI 0 "register_operand" "=vd,vd, vr, vr")
+ (if_then_else:V_VLSI
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" "vm,vm,Wc1,Wc1")
(match_operand 4 "vector_length_operand" "rK,rK, rK, rK")
@@ -3396,9 +3396,9 @@
(match_operand 7 "const_int_operand" " i, i, i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
- (any_int_unop:VI
- (match_operand:VI 3 "register_operand" "vr,vr, vr, vr"))
- (match_operand:VI 2 "vector_merge_operand" "vu, 0, vu, 0")))]
+ (any_int_unop:V_VLSI
+ (match_operand:V_VLSI 3 "register_operand" "vr,vr, vr, vr"))
+ (match_operand:V_VLSI 2 "vector_merge_operand" "vu, 0, vu, 0")))]
"TARGET_VECTOR"
"v<insn>.v\t%0,%3%p1"
[(set_attr "type" "vialu")
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h
index 33916ff0698..2a5baef747b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h
@@ -142,3 +142,11 @@ typedef double v512df __attribute__ ((vector_size (4096)));
for (int i = 0; i < NUM; ++i) \
a[i] = b[i] OP 7; \
}
+
+#define DEF_OP_V(PREFIX, NUM, TYPE, OP) \
+ void __attribute__ ((noinline, noclone)) \
+ PREFIX##_##TYPE##NUM (TYPE *restrict a, TYPE *restrict b) \
+ { \
+ for (int i = 0; i < NUM; ++i) \
+ a[i] = OP b[i]; \
+ }
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/neg-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/neg-1.c
new file mode 100644
index 00000000000..0d723d70e8c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/neg-1.c
@@ -0,0 +1,57 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */
+
+#include "def.h"
+
+DEF_OP_V (neg, 1, int8_t, -)
+DEF_OP_V (neg, 2, int8_t, -)
+DEF_OP_V (neg, 4, int8_t, -)
+DEF_OP_V (neg, 8, int8_t, -)
+DEF_OP_V (neg, 16, int8_t, -)
+DEF_OP_V (neg, 32, int8_t, -)
+DEF_OP_V (neg, 64, int8_t, -)
+DEF_OP_V (neg, 128, int8_t, -)
+DEF_OP_V (neg, 256, int8_t, -)
+DEF_OP_V (neg, 512, int8_t, -)
+DEF_OP_V (neg, 1024, int8_t, -)
+DEF_OP_V (neg, 2048, int8_t, -)
+DEF_OP_V (neg, 4096, int8_t, -)
+
+DEF_OP_V (neg, 1, int16_t, -)
+DEF_OP_V (neg, 2, int16_t, -)
+DEF_OP_V (neg, 4, int16_t, -)
+DEF_OP_V (neg, 8, int16_t, -)
+DEF_OP_V (neg, 16, int16_t, -)
+DEF_OP_V (neg, 32, int16_t, -)
+DEF_OP_V (neg, 64, int16_t, -)
+DEF_OP_V (neg, 128, int16_t, -)
+DEF_OP_V (neg, 256, int16_t, -)
+DEF_OP_V (neg, 512, int16_t, -)
+DEF_OP_V (neg, 1024, int16_t, -)
+DEF_OP_V (neg, 2048, int16_t, -)
+
+DEF_OP_V (neg, 1, int32_t, -)
+DEF_OP_V (neg, 2, int32_t, -)
+DEF_OP_V (neg, 4, int32_t, -)
+DEF_OP_V (neg, 8, int32_t, -)
+DEF_OP_V (neg, 16, int32_t, -)
+DEF_OP_V (neg, 32, int32_t, -)
+DEF_OP_V (neg, 64, int32_t, -)
+DEF_OP_V (neg, 128, int32_t, -)
+DEF_OP_V (neg, 256, int32_t, -)
+DEF_OP_V (neg, 512, int32_t, -)
+DEF_OP_V (neg, 1024, int32_t, -)
+
+DEF_OP_V (neg, 1, int64_t, -)
+DEF_OP_V (neg, 2, int64_t, -)
+DEF_OP_V (neg, 4, int64_t, -)
+DEF_OP_V (neg, 8, int64_t, -)
+DEF_OP_V (neg, 16, int64_t, -)
+DEF_OP_V (neg, 32, int64_t, -)
+DEF_OP_V (neg, 64, int64_t, -)
+DEF_OP_V (neg, 128, int64_t, -)
+DEF_OP_V (neg, 256, int64_t, -)
+DEF_OP_V (neg, 512, int64_t, -)
+
+/* { dg-final { scan-assembler-times {vneg\.v\s+v[0-9]+,\s*v[0-9]+} 42 } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
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