[gcc r13-7695] RISC-V: Fix a bug that causes an error insn.

[gcc r13-7695] RISC-V: Fix a bug that causes an error insn.

[Pan Li]

https://gcc.gnu.org/g:ffd676ef2c9849231626a532343c7ec908558c33

commit r13-7695-gffd676ef2c9849231626a532343c7ec908558c33
Author: yulong <shiyulong@iscas.ac.cn>
Date:   Tue Aug 8 12:12:32 2023 +0800

    RISC-V: Fix a bug that causes an error insn.
    
    I test the following rvv intrinsics.
    vint64m1_t test_vslide1up_vx_i64m1_m(vbool64_t mask, vint64m1_t src, int64_t value, size_t vl) {
      return __riscv_vslide1up_vx_i64m1_m(mask, src, value, vl);
    }
    And I got an error info,t hat is error:
      unrecognizable insn:(insn 17 16 18 2
        (set (reg:RVVMIDI 134 [ _1 ])(if_then_else:RVVMIDI
          (unspec:RVVMF64BI [(reg/v:SI 142 [ vl ])(const_int 2 [x2])(const_int 日 [o])(reg:SI 66 vl)(reg:SI 67 vtype)] UNSPEC_VPREDICATE
       (vec_merge:RVVMIDI (reg:RVVMIDI 134 [ _1 ])(unspec:RVVMIDI [(reg:sI 日 zero)] UNSPEC_VUNDEF)
       (reg/v:RVVMF64BI 137 [ mask ]))
       (unspec:RVVM1DI[(reg:sI 日 zero)] UNSPEC_VUNDEF)))
    
    This patch fix it.
    
    gcc/ChangeLog:
    
            * config/riscv/riscv-v.cc (slide1_sew64_helper): Modify.
    
    gcc/testsuite/ChangeLog:
    
            * gcc.target/riscv/rvv/base/vslide1down-1.c: New test.
            * gcc.target/riscv/rvv/base/vslide1down-2.c: New test.
            * gcc.target/riscv/rvv/base/vslide1down-3.c: New test.
            * gcc.target/riscv/rvv/base/vslide1up-1.c: New test.
            * gcc.target/riscv/rvv/base/vslide1up-2.c: New test.
            * gcc.target/riscv/rvv/base/vslide1up-3.c: New test.

Diff:
---
 gcc/config/riscv/riscv-v.cc                        |  5 ++---
 .../gcc.target/riscv/rvv/base/vslide1down-1.c      | 22 ++++++++++++++++++++++
 .../gcc.target/riscv/rvv/base/vslide1down-2.c      | 22 ++++++++++++++++++++++
 .../gcc.target/riscv/rvv/base/vslide1down-3.c      | 22 ++++++++++++++++++++++
 .../gcc.target/riscv/rvv/base/vslide1up-1.c        | 22 ++++++++++++++++++++++
 .../gcc.target/riscv/rvv/base/vslide1up-2.c        | 22 ++++++++++++++++++++++
 .../gcc.target/riscv/rvv/base/vslide1up-3.c        | 22 ++++++++++++++++++++++
 7 files changed, 134 insertions(+), 3 deletions(-)

diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index 392f5d02e17..722ed27bd26 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -701,9 +701,8 @@ slide1_sew64_helper (int unspec, machine_mode mode, machine_mode demote_mode,
 			     CONSTM1_RTX (demote_mask_mode), merge, temp,
 			     demote_scalar_op2, vl_x2, ta, ma, ops[8]));
 
-  if (rtx_equal_p (ops[1], CONSTM1_RTX (GET_MODE (ops[1]))))
-    return true;
-  else
+  if (!rtx_equal_p (ops[1], CONSTM1_RTX (GET_MODE (ops[1])))
+      && !rtx_equal_p (ops[2], RVV_VUNDEF (GET_MODE (ops[2]))))
     emit_insn (gen_pred_merge (mode, ops[0], ops[2], ops[2], ops[0], ops[1],
 			       force_vector_length_operand (ops[5]), ops[6],
 			       ops[8]));
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vslide1down-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vslide1down-1.c
new file mode 100644
index 00000000000..541745be2a1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vslide1down-1.c
@@ -0,0 +1,22 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_zve64x -mabi=ilp32d -Wno-psabi -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint64m1_t test_vslide1down_vx_i64m1_m(vbool64_t mask, vint64m1_t src, int64_t value, size_t vl) {
+  return __riscv_vslide1down_vx_i64m1_m(mask, src, value, vl);
+}
+
+vint64m2_t test_vslide1down_vx_i64m2_m(vbool32_t mask, vint64m2_t src, int64_t value, size_t vl) {
+  return __riscv_vslide1down_vx_i64m2_m(mask, src, value, vl);
+}
+
+vint64m4_t test_vslide1down_vx_i64m4_m(vbool16_t mask, vint64m4_t src, int64_t value, size_t vl) {
+  return __riscv_vslide1down_vx_i64m4_m(mask, src, value, vl);
+}
+
+vint64m8_t test_vslide1down_vx_i64m8_m(vbool8_t mask, vint64m8_t src, int64_t value, size_t vl) {
+  return __riscv_vslide1down_vx_i64m8_m(mask, src, value, vl);
+}
+
+/* { dg-final { scan-assembler-times {vseti?vli\s+[a-z0-9]+,\s*[a-z0-9]+,\s*e[0-9]+,\s*mf?[1248],\s*t[au],\s*m[au]\s+vslide1down\.[ivxfswum.]+\s+} 4 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vslide1down-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vslide1down-2.c
new file mode 100644
index 00000000000..9b5a240a9e6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vslide1down-2.c
@@ -0,0 +1,22 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_zve64d -mabi=ilp32d -Wno-psabi -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint64m1_t test_vslide1down_vx_i64m1_m(vbool64_t mask, vint64m1_t src, int64_t value, size_t vl) {
+  return __riscv_vslide1down_vx_i64m1_m(mask, src, value, vl);
+}
+
+vint64m2_t test_vslide1down_vx_i64m2_m(vbool32_t mask, vint64m2_t src, int64_t value, size_t vl) {
+  return __riscv_vslide1down_vx_i64m2_m(mask, src, value, vl);
+}
+
+vint64m4_t test_vslide1down_vx_i64m4_m(vbool16_t mask, vint64m4_t src, int64_t value, size_t vl) {
+  return __riscv_vslide1down_vx_i64m4_m(mask, src, value, vl);
+}
+
+vint64m8_t test_vslide1down_vx_i64m8_m(vbool8_t mask, vint64m8_t src, int64_t value, size_t vl) {
+  return __riscv_vslide1down_vx_i64m8_m(mask, src, value, vl);
+}
+
+/* { dg-final { scan-assembler-times {vseti?vli\s+[a-z0-9]+,\s*[a-z0-9]+,\s*e[0-9]+,\s*mf?[1248],\s*t[au],\s*m[au]\s+vslide1down\.[ivxfswum.]+\s+} 4 } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vslide1down-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vslide1down-3.c
new file mode 100644
index 00000000000..7b05c85a243
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vslide1down-3.c
@@ -0,0 +1,22 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_zve64f -mabi=ilp32d -Wno-psabi -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint64m1_t test_vslide1down_vx_i64m1_m(vbool64_t mask, vint64m1_t src, int64_t value, size_t vl) {
+  return __riscv_vslide1down_vx_i64m1_m(mask, src, value, vl);
+}
+
+vint64m2_t test_vslide1down_vx_i64m2_m(vbool32_t mask, vint64m2_t src, int64_t value, size_t vl) {
+  return __riscv_vslide1down_vx_i64m2_m(mask, src, value, vl);
+}
+
+vint64m4_t test_vslide1down_vx_i64m4_m(vbool16_t mask, vint64m4_t src, int64_t value, size_t vl) {
+  return __riscv_vslide1down_vx_i64m4_m(mask, src, value, vl);
+}
+
+vint64m8_t test_vslide1down_vx_i64m8_m(vbool8_t mask, vint64m8_t src, int64_t value, size_t vl) {
+  return __riscv_vslide1down_vx_i64m8_m(mask, src, value, vl);
+}
+
+/* { dg-final { scan-assembler-times {vseti?vli\s+[a-z0-9]+,\s*[a-z0-9]+,\s*e[0-9]+,\s*mf?[1248],\s*t[au],\s*m[au]\s+vslide1down\.[ivxfswum.]+\s+} 4 } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vslide1up-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vslide1up-1.c
new file mode 100644
index 00000000000..74e8e5e63f7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vslide1up-1.c
@@ -0,0 +1,22 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_zve64x -mabi=ilp32d -Wno-psabi -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint64m1_t test_vslide1up_vx_i64m1_m(vbool64_t mask, vint64m1_t src, int64_t value, size_t vl) {
+  return __riscv_vslide1up_vx_i64m1_m(mask, src, value, vl);
+}
+
+vint64m2_t test_vslide1up_vx_i64m2_m(vbool32_t mask, vint64m2_t src, int64_t value, size_t vl) {
+  return __riscv_vslide1up_vx_i64m2_m(mask, src, value, vl);
+}
+
+vint64m4_t test_vslide1up_vx_i64m4_m(vbool16_t mask, vint64m4_t src, int64_t value, size_t vl) {
+  return __riscv_vslide1up_vx_i64m4_m(mask, src, value, vl);
+}
+
+vint64m8_t test_vslide1up_vx_i64m8_m(vbool8_t mask, vint64m8_t src, int64_t value, size_t vl) {
+  return __riscv_vslide1up_vx_i64m8_m(mask, src, value, vl);
+}
+
+/* { dg-final { scan-assembler-times {vseti?vli\s+[a-z0-9]+,\s*[a-z0-9]+,\s*e[0-9]+,\s*mf?[1248],\s*t[au],\s*m[au]\s+vslide1up\.[ivxfswum.]+\s+} 4 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vslide1up-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vslide1up-2.c
new file mode 100644
index 00000000000..e7e2ee950c7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vslide1up-2.c
@@ -0,0 +1,22 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_zve64d -mabi=ilp32d -Wno-psabi -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint64m1_t test_vslide1up_vx_i64m1_m(vbool64_t mask, vint64m1_t src, int64_t value, size_t vl) {
+  return __riscv_vslide1up_vx_i64m1_m(mask, src, value, vl);
+}
+
+vint64m2_t test_vslide1up_vx_i64m2_m(vbool32_t mask, vint64m2_t src, int64_t value, size_t vl) {
+  return __riscv_vslide1up_vx_i64m2_m(mask, src, value, vl);
+}
+
+vint64m4_t test_vslide1up_vx_i64m4_m(vbool16_t mask, vint64m4_t src, int64_t value, size_t vl) {
+  return __riscv_vslide1up_vx_i64m4_m(mask, src, value, vl);
+}
+
+vint64m8_t test_vslide1up_vx_i64m8_m(vbool8_t mask, vint64m8_t src, int64_t value, size_t vl) {
+  return __riscv_vslide1up_vx_i64m8_m(mask, src, value, vl);
+}
+
+/* { dg-final { scan-assembler-times {vseti?vli\s+[a-z0-9]+,\s*[a-z0-9]+,\s*e[0-9]+,\s*mf?[1248],\s*t[au],\s*m[au]\s+vslide1up\.[ivxfswum.]+\s+} 4 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vslide1up-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vslide1up-3.c
new file mode 100644
index 00000000000..b0b3af24e64
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vslide1up-3.c
@@ -0,0 +1,22 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_zve64f -mabi=ilp32d -Wno-psabi -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint64m1_t test_vslide1up_vx_i64m1_m(vbool64_t mask, vint64m1_t src, int64_t value, size_t vl) {
+  return __riscv_vslide1up_vx_i64m1_m(mask, src, value, vl);
+}
+
+vint64m2_t test_vslide1up_vx_i64m2_m(vbool32_t mask, vint64m2_t src, int64_t value, size_t vl) {
+  return __riscv_vslide1up_vx_i64m2_m(mask, src, value, vl);
+}
+
+vint64m4_t test_vslide1up_vx_i64m4_m(vbool16_t mask, vint64m4_t src, int64_t value, size_t vl) {
+  return __riscv_vslide1up_vx_i64m4_m(mask, src, value, vl);
+}
+
+vint64m8_t test_vslide1up_vx_i64m8_m(vbool8_t mask, vint64m8_t src, int64_t value, size_t vl) {
+  return __riscv_vslide1up_vx_i64m8_m(mask, src, value, vl);
+}
+
+/* { dg-final { scan-assembler-times {vseti?vli\s+[a-z0-9]+,\s*[a-z0-9]+,\s*e[0-9]+,\s*mf?[1248],\s*t[au],\s*m[au]\s+vslide1up\.[ivxfswum.]+\s+} 4 } } */