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* [gcc(refs/vendors/riscv/heads/gcc-13-with-riscv-opts)] RISC-V: Refactor RVV frm_mode attr for rounding mode intrinsic
@ 2023-08-21 21:28 Jeff Law
0 siblings, 0 replies; only message in thread
From: Jeff Law @ 2023-08-21 21:28 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:3e9622d644388c65b87255aaf5dd9ae9915f9a3c
commit 3e9622d644388c65b87255aaf5dd9ae9915f9a3c
Author: Pan Li <pan2.li@intel.com>
Date: Sun Aug 6 11:10:23 2023 +0800
RISC-V: Refactor RVV frm_mode attr for rounding mode intrinsic
The frm_mode attr has some assumptions for each define insn as below.
1. The define insn has at least 9 operands.
2. The operands[9] must be frm reg.
3. The operands[9] must be const int.
Actually, the frm operand can be operands[8], operands[9] or
operands[10], and not all the define insn has frm operands.
This patch would like to refactor frm and eliminate the above
assumptions, as well as unblock the underlying rounding mode intrinsic
API support.
After refactor, the default frm will be none, and the selected insn type
will be dyn. For the floating point which honors the frm, we will
set the frm_mode attr explicitly in define_insn.
Signed-off-by: Pan Li <pan2.li@intel.com>
Co-Authored-by: Kito Cheng <kito.cheng@sifive.com>
gcc/ChangeLog:
* config/riscv/riscv-protos.h
(enum floating_point_rounding_mode): Add NONE, DYN_EXIT and DYN_CALL.
(get_frm_mode): New declaration.
* config/riscv/riscv-v.cc (get_frm_mode): New function to get frm mode.
* config/riscv/riscv-vector-builtins.cc
(function_expander::use_ternop_insn): Take care of frm reg.
* config/riscv/riscv.cc (riscv_static_frm_mode_p): Migrate to FRM_XXX.
(riscv_emit_frm_mode_set): Ditto.
(riscv_emit_mode_set): Ditto.
(riscv_frm_adjust_mode_after_call): Ditto.
(riscv_frm_mode_needed): Ditto.
(riscv_frm_mode_after): Ditto.
(riscv_mode_entry): Ditto.
(riscv_mode_exit): Ditto.
* config/riscv/riscv.h (NUM_MODES_FOR_MODE_SWITCHING): Ditto.
* config/riscv/vector.md
(rne,rtz,rdn,rup,rmm,dyn,dyn_exit,dyn_call,none): Removed
(symbol_ref): * config/riscv/vector.md: Set frm_mode attr explicitly.
(cherry picked from commit 4cede0de9a19ee1a911b27dbe0916e67f1f3d7c9)
Diff:
---
gcc/config/riscv/riscv-protos.h | 4 +
gcc/config/riscv/riscv-v.cc | 29 +++++
gcc/config/riscv/riscv-vector-builtins.cc | 22 +++-
gcc/config/riscv/riscv.cc | 46 ++++----
gcc/config/riscv/riscv.h | 2 +-
gcc/config/riscv/vector.md | 172 ++++++++++++++++++++----------
6 files changed, 186 insertions(+), 89 deletions(-)
diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
index ac9c4b02f172..2fbed04ff84c 100644
--- a/gcc/config/riscv/riscv-protos.h
+++ b/gcc/config/riscv/riscv-protos.h
@@ -349,8 +349,12 @@ enum floating_point_rounding_mode
FRM_DYN = 7, /* Aka 0b111. */
FRM_STATIC_MIN = FRM_RNE,
FRM_STATIC_MAX = FRM_RMM,
+ FRM_DYN_EXIT = 8,
+ FRM_DYN_CALL = 9,
+ FRM_NONE = 10,
};
+enum floating_point_rounding_mode get_frm_mode (rtx);
opt_machine_mode vectorize_related_mode (machine_mode, scalar_mode,
poly_uint64);
unsigned int autovectorize_vector_modes (vec<machine_mode> *, bool);
diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index 0bea04c1967e..c9f0a4a9e7b0 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -112,6 +112,7 @@ public:
{
m_has_fp_rounding_mode_p = true;
m_fp_rounding_mode = mode;
+ gcc_assert (mode <= FRM_DYN);
}
void add_output_operand (rtx x, machine_mode mode)
@@ -1590,6 +1591,34 @@ expand_const_vector (rtx target, rtx src)
gcc_unreachable ();
}
+/* Get the frm mode with given CONST_INT rtx, the default mode is
+ FRM_DYN. */
+enum floating_point_rounding_mode
+get_frm_mode (rtx operand)
+{
+ gcc_assert (CONST_INT_P (operand));
+
+ switch (INTVAL (operand))
+ {
+ case FRM_RNE:
+ return FRM_RNE;
+ case FRM_RTZ:
+ return FRM_RTZ;
+ case FRM_RDN:
+ return FRM_RDN;
+ case FRM_RUP:
+ return FRM_RUP;
+ case FRM_RMM:
+ return FRM_RMM;
+ case FRM_DYN:
+ return FRM_DYN;
+ default:
+ gcc_unreachable ();
+ }
+
+ gcc_unreachable ();
+}
+
/* Expand a pre-RA RVV data move from SRC to DEST.
It expands move for RVV fractional vector modes. */
bool
diff --git a/gcc/config/riscv/riscv-vector-builtins.cc b/gcc/config/riscv/riscv-vector-builtins.cc
index 528dca7ae855..abab06c00eda 100644
--- a/gcc/config/riscv/riscv-vector-builtins.cc
+++ b/gcc/config/riscv/riscv-vector-builtins.cc
@@ -3730,17 +3730,29 @@ function_expander::use_ternop_insn (bool vd_accum_p, insn_code icode)
}
for (int argno = arg_offset; argno < call_expr_nargs (exp); argno++)
- add_input_operand (argno);
+ {
+ if (base->has_rounding_mode_operand_p ()
+ && argno == call_expr_nargs (exp) - 2)
+ {
+ /* Since the rounding mode argument position is not consistent with
+ the instruction pattern, we need to skip rounding mode argument
+ here. */
+ continue;
+ }
+ add_input_operand (argno);
+ }
add_input_operand (Pmode, get_tail_policy_for_pred (pred));
add_input_operand (Pmode, get_mask_policy_for_pred (pred));
add_input_operand (Pmode, get_avl_type_rtx (avl_type::NONVLMAX));
- /* TODO: Currently, we don't support intrinsic that is modeling rounding mode.
- We add default rounding mode for the intrinsics that didn't model rounding
- mode yet. */
+ if (base->has_rounding_mode_operand_p ())
+ add_input_operand (call_expr_nargs (exp) - 2);
+
+ /* The RVV floating-point only support dynamic rounding mode in the
+ FRM register. */
if (opno != insn_data[icode].n_generator_args)
- add_input_operand (Pmode, const0_rtx);
+ add_input_operand (Pmode, gen_int_mode (riscv_vector::FRM_DYN, Pmode));
return generate_insn (icode);
}
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 01add5b9d8c6..1224972bd351 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -8053,11 +8053,11 @@ riscv_static_frm_mode_p (int mode)
{
switch (mode)
{
- case FRM_MODE_RDN:
- case FRM_MODE_RUP:
- case FRM_MODE_RTZ:
- case FRM_MODE_RMM:
- case FRM_MODE_RNE:
+ case riscv_vector::FRM_RDN:
+ case riscv_vector::FRM_RUP:
+ case riscv_vector::FRM_RTZ:
+ case riscv_vector::FRM_RMM:
+ case riscv_vector::FRM_RNE:
return true;
default:
return false;
@@ -8073,28 +8073,24 @@ riscv_emit_frm_mode_set (int mode, int prev_mode)
{
rtx backup_reg = DYNAMIC_FRM_RTL (cfun);
- if (prev_mode == FRM_MODE_DYN_CALL)
+ if (prev_mode == riscv_vector::FRM_DYN_CALL)
emit_insn (gen_frrmsi (backup_reg)); /* Backup frm when DYN_CALL. */
if (mode != prev_mode)
{
- /* TODO: By design, FRM_MODE_xxx used by mode switch which is
- different from the FRM value like FRM_RTZ defined in
- riscv-protos.h. When mode switching we actually need a conversion
- function to convert the mode of mode switching to the actual
- FRM value like FRM_RTZ. For now, the value between the mode of
- mode swith and the FRM value in riscv-protos.h take the same value,
- and then we leverage this assumption when emit. */
rtx frm = gen_int_mode (mode, SImode);
- if (mode == FRM_MODE_DYN_CALL && prev_mode != FRM_MODE_DYN)
+ if (mode == riscv_vector::FRM_DYN_CALL
+ && prev_mode != riscv_vector::FRM_DYN)
/* No need to emit when prev mode is DYN already. */
emit_insn (gen_fsrmsi_restore_volatile (backup_reg));
- else if (mode == FRM_MODE_DYN_EXIT && STATIC_FRM_P (cfun)
- && prev_mode != FRM_MODE_DYN && prev_mode != FRM_MODE_DYN_CALL)
+ else if (mode == riscv_vector::FRM_DYN_EXIT && STATIC_FRM_P (cfun)
+ && prev_mode != riscv_vector::FRM_DYN
+ && prev_mode != riscv_vector::FRM_DYN_CALL)
/* No need to emit when prev mode is DYN or DYN_CALL already. */
emit_insn (gen_fsrmsi_restore_volatile (backup_reg));
- else if (mode == FRM_MODE_DYN && prev_mode != FRM_MODE_DYN_CALL)
+ else if (mode == riscv_vector::FRM_DYN
+ && prev_mode != riscv_vector::FRM_DYN_CALL)
/* Restore frm value from backup when switch to DYN mode. */
emit_insn (gen_fsrmsi_restore (backup_reg));
else if (riscv_static_frm_mode_p (mode))
@@ -8123,7 +8119,7 @@ riscv_emit_mode_set (int entity, int mode, int prev_mode,
}
}
-/* Adjust the FRM_MODE_NONE insn after a call to FRM_MODE_DYN for the
+/* Adjust the FRM_NONE insn after a call to FRM_DYN for the
underlying emit. */
static int
@@ -8132,7 +8128,7 @@ riscv_frm_adjust_mode_after_call (rtx_insn *cur_insn, int mode)
rtx_insn *insn = prev_nonnote_nondebug_insn_bb (cur_insn);
if (insn && CALL_P (insn))
- return FRM_MODE_DYN;
+ return riscv_vector::FRM_DYN;
return mode;
}
@@ -8183,12 +8179,12 @@ riscv_frm_mode_needed (rtx_insn *cur_insn, int code)
if (!insn)
riscv_frm_emit_after_bb_end (cur_insn);
- return FRM_MODE_DYN_CALL;
+ return riscv_vector::FRM_DYN_CALL;
}
- int mode = code >= 0 ? get_attr_frm_mode (cur_insn) : FRM_MODE_NONE;
+ int mode = code >= 0 ? get_attr_frm_mode (cur_insn) : riscv_vector::FRM_NONE;
- if (mode == FRM_MODE_NONE)
+ if (mode == riscv_vector::FRM_NONE)
/* After meet a call, we need to backup the frm because it may be
updated during the call. Here, for each insn, we will check if
the previous insn is a call or not. When previous insn is call,
@@ -8296,7 +8292,7 @@ riscv_frm_mode_after (rtx_insn *insn, int mode)
return mode;
if (frm_unknown_dynamic_p (insn))
- return FRM_MODE_DYN;
+ return riscv_vector::FRM_DYN;
if (recog_memoized (insn) < 0)
return mode;
@@ -8338,7 +8334,7 @@ riscv_mode_entry (int entity)
/* According to RVV 1.0 spec, all vector floating-point operations use
the dynamic rounding mode in the frm register. Likewise in other
similar places. */
- return FRM_MODE_DYN;
+ return riscv_vector::FRM_DYN;
}
default:
gcc_unreachable ();
@@ -8356,7 +8352,7 @@ riscv_mode_exit (int entity)
case RISCV_VXRM:
return VXRM_MODE_NONE;
case RISCV_FRM:
- return FRM_MODE_DYN_EXIT;
+ return riscv_vector::FRM_DYN_EXIT;
default:
gcc_unreachable ();
}
diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h
index 643e7ea73304..746101ea933a 100644
--- a/gcc/config/riscv/riscv.h
+++ b/gcc/config/riscv/riscv.h
@@ -1120,6 +1120,6 @@ extern void riscv_remove_unneeded_save_restore_calls (void);
/* Mode switching (Lazy code motion) for RVV rounding mode instructions. */
#define OPTIMIZE_MODE_SWITCHING(ENTITY) (TARGET_VECTOR)
-#define NUM_MODES_FOR_MODE_SWITCHING {VXRM_MODE_NONE, FRM_MODE_NONE}
+#define NUM_MODES_FOR_MODE_SWITCHING {VXRM_MODE_NONE, riscv_vector::FRM_NONE}
#endif /* ! GCC_RISCV_H */
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index 65b5fe456ed2..cf37b4729302 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -865,28 +865,10 @@
(const_string "none")))
;; Defines rounding mode of an floating-point operation.
-(define_attr "frm_mode" "rne,rtz,rdn,rup,rmm,dyn,dyn_exit,dyn_call,none"
+(define_attr "frm_mode" ""
(cond [(eq_attr "type" "vfalu,vfwalu,vfmul,vfdiv,vfwmul")
- (cond
- [(match_test "INTVAL (operands[9]) == riscv_vector::FRM_RNE")
- (const_string "rne")
-
- (match_test "INTVAL (operands[9]) == riscv_vector::FRM_RTZ")
- (const_string "rtz")
-
- (match_test "INTVAL (operands[9]) == riscv_vector::FRM_RDN")
- (const_string "rdn")
-
- (match_test "INTVAL (operands[9]) == riscv_vector::FRM_RUP")
- (const_string "rup")
-
- (match_test "INTVAL (operands[9]) == riscv_vector::FRM_RMM")
- (const_string "rmm")
-
- (match_test "INTVAL (operands[9]) == riscv_vector::FRM_DYN")
- (const_string "dyn")]
- (const_string "none"))]
- (const_string "none")))
+ (symbol_ref "riscv_vector::FRM_DYN")]
+ (symbol_ref "riscv_vector::FRM_NONE")))
;; -----------------------------------------------------------------
;; ---- Miscellaneous Operations
@@ -6021,7 +6003,9 @@
"TARGET_VECTOR"
"vf<insn>.vv\t%0,%3,%4%p1"
[(set_attr "type" "<float_insn_type>")
- (set_attr "mode" "<MODE>")])
+ (set_attr "mode" "<MODE>")
+ (set (attr "frm_mode")
+ (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "@pred_<optab><mode>"
[(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr")
@@ -6064,7 +6048,9 @@
"TARGET_VECTOR"
"vf<insn>.vf\t%0,%3,%4%p1"
[(set_attr "type" "<float_insn_type>")
- (set_attr "mode" "<MODE>")])
+ (set_attr "mode" "<MODE>")
+ (set (attr "frm_mode")
+ (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "@pred_<optab><mode>_scalar"
[(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr")
@@ -6108,7 +6094,9 @@
"TARGET_VECTOR"
"vf<insn>.vf\t%0,%3,%4%p1"
[(set_attr "type" "<float_insn_type>")
- (set_attr "mode" "<MODE>")])
+ (set_attr "mode" "<MODE>")
+ (set (attr "frm_mode")
+ (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "@pred_<optab><mode>_reverse_scalar"
[(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr")
@@ -6131,7 +6119,9 @@
"TARGET_VECTOR"
"vfr<insn>.vf\t%0,%3,%4%p1"
[(set_attr "type" "<float_insn_type>")
- (set_attr "mode" "<MODE>")])
+ (set_attr "mode" "<MODE>")
+ (set (attr "frm_mode")
+ (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "@pred_<copysign><mode>"
[(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr")
@@ -6279,7 +6269,9 @@
(set_attr "vl_op_idx" "5")
(set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
(set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
- (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))])
+ (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))
+ (set (attr "frm_mode")
+ (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "*pred_<macc_msac><mode>"
[(set (match_operand:VF 0 "register_operand" "=vd, ?&vd, vr, ?&vr")
@@ -6312,7 +6304,9 @@
(set_attr "vl_op_idx" "5")
(set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
(set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
- (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))])
+ (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))
+ (set (attr "frm_mode")
+ (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
(define_insn_and_rewrite "*pred_mul_<optab><mode>"
[(set (match_operand:VF 0 "register_operand" "=&vr")
@@ -6343,7 +6337,9 @@
riscv_vector::prepare_ternary_operands (operands, true);
}
[(set_attr "type" "vfmuladd")
- (set_attr "mode" "<MODE>")])
+ (set_attr "mode" "<MODE>")
+ (set (attr "frm_mode")
+ (symbol_ref "riscv_vector::get_frm_mode (operands[10])"))])
(define_expand "@pred_mul_<optab><mode>_scalar"
[(set (match_operand:VF 0 "register_operand")
@@ -6400,7 +6396,9 @@
(set_attr "vl_op_idx" "5")
(set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
(set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
- (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))])
+ (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))
+ (set (attr "frm_mode")
+ (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "*pred_<macc_msac><mode>_scalar"
[(set (match_operand:VF 0 "register_operand" "=vd, ?&vd, vr, ?&vr")
@@ -6434,7 +6432,9 @@
(set_attr "vl_op_idx" "5")
(set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
(set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
- (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))])
+ (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))
+ (set (attr "frm_mode")
+ (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
(define_insn_and_rewrite "*pred_mul_<optab><mode>_scalar"
[(set (match_operand:VF 0 "register_operand" "=&vr")
@@ -6465,7 +6465,9 @@
riscv_vector::prepare_ternary_operands (operands, true);
}
[(set_attr "type" "vfmuladd")
- (set_attr "mode" "<MODE>")])
+ (set_attr "mode" "<MODE>")
+ (set (attr "frm_mode")
+ (symbol_ref "riscv_vector::get_frm_mode (operands[10])"))])
(define_expand "@pred_mul_neg_<optab><mode>"
[(set (match_operand:VF 0 "register_operand")
@@ -6524,7 +6526,9 @@
(set_attr "vl_op_idx" "5")
(set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
(set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
- (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))])
+ (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))
+ (set (attr "frm_mode")
+ (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "*pred_<nmsac_nmacc><mode>"
[(set (match_operand:VF 0 "register_operand" "=vd, ?&vd, vr, ?&vr")
@@ -6558,7 +6562,9 @@
(set_attr "vl_op_idx" "5")
(set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
(set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
- (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))])
+ (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))
+ (set (attr "frm_mode")
+ (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
(define_insn_and_rewrite "*pred_mul_neg_<optab><mode>"
[(set (match_operand:VF 0 "register_operand" "=&vr")
@@ -6590,7 +6596,9 @@
riscv_vector::prepare_ternary_operands (operands, true);
}
[(set_attr "type" "vfmuladd")
- (set_attr "mode" "<MODE>")])
+ (set_attr "mode" "<MODE>")
+ (set (attr "frm_mode")
+ (symbol_ref "riscv_vector::get_frm_mode (operands[10])"))])
(define_expand "@pred_mul_neg_<optab><mode>_scalar"
[(set (match_operand:VF 0 "register_operand")
@@ -6649,7 +6657,9 @@
(set_attr "vl_op_idx" "5")
(set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
(set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
- (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))])
+ (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))
+ (set (attr "frm_mode")
+ (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "*pred_<nmsac_nmacc><mode>_scalar"
[(set (match_operand:VF 0 "register_operand" "=vd, ?&vd, vr, ?&vr")
@@ -6684,7 +6694,9 @@
(set_attr "vl_op_idx" "5")
(set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
(set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
- (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))])
+ (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))
+ (set (attr "frm_mode")
+ (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
(define_insn_and_rewrite "*pred_mul_neg_<optab><mode>_scalar"
[(set (match_operand:VF 0 "register_operand" "=&vr")
@@ -6716,7 +6728,9 @@
riscv_vector::prepare_ternary_operands (operands, true);
}
[(set_attr "type" "vfmuladd")
- (set_attr "mode" "<MODE>")])
+ (set_attr "mode" "<MODE>")
+ (set (attr "frm_mode")
+ (symbol_ref "riscv_vector::get_frm_mode (operands[10])"))])
;; -------------------------------------------------------------------------------
;; ---- Predicated floating-point unary operations
@@ -6752,7 +6766,9 @@
(set_attr "vl_op_idx" "4")
(set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[5])"))
(set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])"))
- (set (attr "avl_type") (symbol_ref "INTVAL (operands[7])"))])
+ (set (attr "avl_type") (symbol_ref "INTVAL (operands[7])"))
+ (set (attr "frm_mode")
+ (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))])
(define_insn "@pred_<optab><mode>"
[(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr")
@@ -6846,7 +6862,9 @@
"TARGET_VECTOR"
"vfw<insn>.vv\t%0,%3,%4%p1"
[(set_attr "type" "vf<widen_binop_insn_type>")
- (set_attr "mode" "<V_DOUBLE_TRUNC>")])
+ (set_attr "mode" "<V_DOUBLE_TRUNC>")
+ (set (attr "frm_mode")
+ (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "@pred_dual_widen_<optab><mode>_scalar"
[(set (match_operand:VWEXTF 0 "register_operand" "=&vr, &vr")
@@ -6871,7 +6889,9 @@
"TARGET_VECTOR"
"vfw<insn>.vf\t%0,%3,%4%p1"
[(set_attr "type" "vf<widen_binop_insn_type>")
- (set_attr "mode" "<V_DOUBLE_TRUNC>")])
+ (set_attr "mode" "<V_DOUBLE_TRUNC>")
+ (set (attr "frm_mode")
+ (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "@pred_single_widen_add<mode>"
[(set (match_operand:VWEXTF 0 "register_operand" "=&vr, &vr")
@@ -6894,7 +6914,9 @@
"TARGET_VECTOR"
"vfwadd.wv\t%0,%3,%4%p1"
[(set_attr "type" "vfwalu")
- (set_attr "mode" "<V_DOUBLE_TRUNC>")])
+ (set_attr "mode" "<V_DOUBLE_TRUNC>")
+ (set (attr "frm_mode")
+ (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "@pred_single_widen_sub<mode>"
[(set (match_operand:VWEXTF 0 "register_operand" "=&vr, &vr")
@@ -6917,7 +6939,9 @@
"TARGET_VECTOR"
"vfwsub.wv\t%0,%3,%4%p1"
[(set_attr "type" "vfwalu")
- (set_attr "mode" "<V_DOUBLE_TRUNC>")])
+ (set_attr "mode" "<V_DOUBLE_TRUNC>")
+ (set (attr "frm_mode")
+ (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "@pred_single_widen_<plus_minus:optab><mode>_scalar"
[(set (match_operand:VWEXTF 0 "register_operand" "=&vr, &vr")
@@ -6941,7 +6965,9 @@
"TARGET_VECTOR"
"vfw<insn>.wf\t%0,%3,%4%p1"
[(set_attr "type" "vf<widen_binop_insn_type>")
- (set_attr "mode" "<V_DOUBLE_TRUNC>")])
+ (set_attr "mode" "<V_DOUBLE_TRUNC>")
+ (set (attr "frm_mode")
+ (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
;; -------------------------------------------------------------------------------
;; ---- Predicated widen floating-point ternary operations
@@ -6974,7 +7000,9 @@
"TARGET_VECTOR"
"vfw<macc_msac>.vv\t%0,%3,%4%p1"
[(set_attr "type" "vfwmuladd")
- (set_attr "mode" "<V_DOUBLE_TRUNC>")])
+ (set_attr "mode" "<V_DOUBLE_TRUNC>")
+ (set (attr "frm_mode")
+ (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "@pred_widen_mul_<optab><mode>_scalar"
[(set (match_operand:VWEXTF 0 "register_operand" "=&vr")
@@ -7001,7 +7029,9 @@
"TARGET_VECTOR"
"vfw<macc_msac>.vf\t%0,%3,%4%p1"
[(set_attr "type" "vfwmuladd")
- (set_attr "mode" "<V_DOUBLE_TRUNC>")])
+ (set_attr "mode" "<V_DOUBLE_TRUNC>")
+ (set (attr "frm_mode")
+ (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "@pred_widen_mul_neg_<optab><mode>"
[(set (match_operand:VWEXTF 0 "register_operand" "=&vr")
@@ -7028,7 +7058,9 @@
"TARGET_VECTOR"
"vfw<nmsac_nmacc>.vv\t%0,%3,%4%p1"
[(set_attr "type" "vfwmuladd")
- (set_attr "mode" "<V_DOUBLE_TRUNC>")])
+ (set_attr "mode" "<V_DOUBLE_TRUNC>")
+ (set (attr "frm_mode")
+ (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "@pred_widen_mul_neg_<optab><mode>_scalar"
[(set (match_operand:VWEXTF 0 "register_operand" "=&vr")
@@ -7056,7 +7088,9 @@
"TARGET_VECTOR"
"vfw<nmsac_nmacc>.vf\t%0,%3,%4%p1"
[(set_attr "type" "vfwmuladd")
- (set_attr "mode" "<V_DOUBLE_TRUNC>")])
+ (set_attr "mode" "<V_DOUBLE_TRUNC>")
+ (set (attr "frm_mode")
+ (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
;; -------------------------------------------------------------------------------
;; ---- Predicated floating-point comparison operations
@@ -7366,7 +7400,9 @@
"TARGET_VECTOR"
"vfcvt.x<v_su>.f.v\t%0,%3%p1"
[(set_attr "type" "vfcvtftoi")
- (set_attr "mode" "<MODE>")])
+ (set_attr "mode" "<MODE>")
+ (set (attr "frm_mode")
+ (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))])
(define_insn "@pred_<fix_cvt><mode>"
[(set (match_operand:<VCONVERT> 0 "register_operand" "=vd, vd, vr, vr")
@@ -7406,7 +7442,9 @@
"TARGET_VECTOR"
"vfcvt.f.x<u>.v\t%0,%3%p1"
[(set_attr "type" "vfcvtitof")
- (set_attr "mode" "<MODE>")])
+ (set_attr "mode" "<MODE>")
+ (set (attr "frm_mode")
+ (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))])
;; -------------------------------------------------------------------------------
;; ---- Predicated floating-point widen conversions
@@ -7434,7 +7472,9 @@
"TARGET_VECTOR"
"vfwcvt.x<v_su>.f.v\t%0,%3%p1"
[(set_attr "type" "vfwcvtftoi")
- (set_attr "mode" "<VNCONVERT>")])
+ (set_attr "mode" "<VNCONVERT>")
+ (set (attr "frm_mode")
+ (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))])
(define_insn "@pred_widen_<fix_cvt><mode>"
[(set (match_operand:VWCONVERTI 0 "register_operand" "=&vr, &vr")
@@ -7519,7 +7559,9 @@
"TARGET_VECTOR"
"vfncvt.x<v_su>.f.w\t%0,%3%p1"
[(set_attr "type" "vfncvtftoi")
- (set_attr "mode" "<VNCONVERT>")])
+ (set_attr "mode" "<VNCONVERT>")
+ (set (attr "frm_mode")
+ (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))])
(define_insn "@pred_narrow_<fix_cvt><mode>"
[(set (match_operand:<VNCONVERT> 0 "register_operand" "=vd, vd, vr, vr, &vr, &vr")
@@ -7559,7 +7601,9 @@
"TARGET_VECTOR"
"vfncvt.f.x<u>.w\t%0,%3%p1"
[(set_attr "type" "vfncvtitof")
- (set_attr "mode" "<VNCONVERT>")])
+ (set_attr "mode" "<VNCONVERT>")
+ (set (attr "frm_mode")
+ (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))])
(define_insn "@pred_trunc<mode>"
[(set (match_operand:<V_DOUBLE_TRUNC> 0 "register_operand" "=vd, vd, vr, vr, &vr, &vr")
@@ -7580,7 +7624,9 @@
"TARGET_VECTOR"
"vfncvt.f.f.w\t%0,%3%p1"
[(set_attr "type" "vfncvtftof")
- (set_attr "mode" "<V_DOUBLE_TRUNC>")])
+ (set_attr "mode" "<V_DOUBLE_TRUNC>")
+ (set (attr "frm_mode")
+ (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))])
(define_insn "@pred_rod_trunc<mode>"
[(set (match_operand:<V_DOUBLE_TRUNC> 0 "register_operand" "=vd, vd, vr, vr, &vr, &vr")
@@ -7860,7 +7906,9 @@
"TARGET_VECTOR"
"vfred<order>sum.vs\t%0,%3,%4%p1"
[(set_attr "type" "vfred<order>")
- (set_attr "mode" "<VHF:MODE>")])
+ (set_attr "mode" "<VHF:MODE>")
+ (set (attr "frm_mode")
+ (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))])
;; Float Ordered Reduction Sum for SF
(define_insn "@pred_reduc_plus<order><VSF:mode><VSF_LMUL1:mode>"
@@ -7886,7 +7934,9 @@
"TARGET_VECTOR"
"vfred<order>sum.vs\t%0,%3,%4%p1"
[(set_attr "type" "vfred<order>")
- (set_attr "mode" "<VSF:MODE>")])
+ (set_attr "mode" "<VSF:MODE>")
+ (set (attr "frm_mode")
+ (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))])
;; Float Ordered Reduction Sum for DF
(define_insn "@pred_reduc_plus<order><VDF:mode><VDF_LMUL1:mode>"
@@ -7912,7 +7962,9 @@
"TARGET_VECTOR"
"vfred<order>sum.vs\t%0,%3,%4%p1"
[(set_attr "type" "vfred<order>")
- (set_attr "mode" "<VDF:MODE>")])
+ (set_attr "mode" "<VDF:MODE>")
+ (set (attr "frm_mode")
+ (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))])
;; Float Widen Reduction for HF, aka SF = HF op SF
(define_insn "@pred_widen_reduc_plus<order><VHF:mode><VSF_LMUL1:mode>"
@@ -7934,7 +7986,9 @@
"TARGET_VECTOR"
"vfwred<order>sum.vs\t%0,%3,%4%p1"
[(set_attr "type" "vfwred<order>")
- (set_attr "mode" "<VHF:MODE>")])
+ (set_attr "mode" "<VHF:MODE>")
+ (set (attr "frm_mode")
+ (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))])
;; Float Widen Reduction for SF, aka DF = SF * DF
(define_insn "@pred_widen_reduc_plus<order><VSF:mode><VDF_LMUL1:mode>"
@@ -7956,7 +8010,9 @@
"TARGET_VECTOR"
"vfwred<order>sum.vs\t%0,%3,%4%p1"
[(set_attr "type" "vfwred<order>")
- (set_attr "mode" "<VSF:MODE>")])
+ (set_attr "mode" "<VSF:MODE>")
+ (set (attr "frm_mode")
+ (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))])
;; -------------------------------------------------------------------------------
;; ---- Predicated permutation operations
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2023-08-21 21:28 [gcc(refs/vendors/riscv/heads/gcc-13-with-riscv-opts)] RISC-V: Refactor RVV frm_mode attr for rounding mode intrinsic Jeff Law
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