From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 2119) id 044CC385B800; Mon, 21 Aug 2023 21:28:13 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 044CC385B800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1692653293; bh=WLKXZ4wWxwUwxY7iZ/nLow//j3d22rdU40mxju3dg9A=; h=From:To:Subject:Date:From; b=uNyjOd4fkDygN2mI74ZOVlMnbe7eVBmxVf+qHAkvxOKhu+za8qC3NHrXBay11iXNL OMPI96lRKwxT3DCWwR/gRgmaP8+1U8ixDj2DuCcFlmp7B4t/QA2k3Bax63wbYLTpxy bFIOasPHtpXNwERD/8814V+cim5CWlwcAE+pBJ7E= Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Jeff Law To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/vendors/riscv/heads/gcc-13-with-riscv-opts)] RISC-V: Add missing modes to the iterators X-Act-Checkin: gcc X-Git-Author: Juzhe-Zhong X-Git-Refname: refs/vendors/riscv/heads/gcc-13-with-riscv-opts X-Git-Oldrev: 3e9622d644388c65b87255aaf5dd9ae9915f9a3c X-Git-Newrev: 32a831ab3feaf8ed6bad73ab48c2ec5f2104d682 Message-Id: <20230821212813.044CC385B800@sourceware.org> Date: Mon, 21 Aug 2023 21:28:13 +0000 (GMT) List-Id: https://gcc.gnu.org/g:32a831ab3feaf8ed6bad73ab48c2ec5f2104d682 commit 32a831ab3feaf8ed6bad73ab48c2ec5f2104d682 Author: Juzhe-Zhong Date: Thu Aug 10 16:55:18 2023 +0800 RISC-V: Add missing modes to the iterators gcc/ChangeLog: * config/riscv/vector-iterators.md: Add missing modes. (cherry picked from commit 6bdbf1722a312b90a48dea19af545815f0069e86) Diff: --- gcc/config/riscv/vector-iterators.md | 3 +++ 1 file changed, 3 insertions(+) diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md index 14829989e09e..30808ceb241b 100644 --- a/gcc/config/riscv/vector-iterators.md +++ b/gcc/config/riscv/vector-iterators.md @@ -468,6 +468,7 @@ (RVVM8DF "TARGET_VECTOR_ELEN_FP_64") (RVVM4DF "TARGET_VECTOR_ELEN_FP_64") (RVVM2DF "TARGET_VECTOR_ELEN_FP_64") (RVVM1DF "TARGET_VECTOR_ELEN_FP_64") + (V1HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16") (V2HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16") (V4HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16") (V8HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16") @@ -479,6 +480,7 @@ (V512HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 1024") (V1024HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 2048") (V2048HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 4096") + (V1SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32") (V2SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32") (V4SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32") (V8SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32") @@ -489,6 +491,7 @@ (V256SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 1024") (V512SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 2048") (V1024SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 4096") + (V1DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64") (V2DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64") (V4DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64") (V8DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 64")