From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 2119) id 027413858CD1; Mon, 21 Aug 2023 21:31:36 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 027413858CD1 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1692653496; bh=Xu65VFb8m1EhH8ed5KcChIzK2vPmvQxsBsmj1AaemyU=; h=From:To:Subject:Date:From; b=iZ6eeRhvkNgwhok6aayym3mGqx3nZev8844pJE2Vx6ruW/YaZJJKoTvp/FpQmPk7k EBV8yyEmYNZdFiPMPlXld1+k31MKbKYH9pJLIWnBjF+wAXNeifMphKmwTJehcugmes hWKznr6LBmuzi6g74V460m2Z3tjB4SDSxnwZfwZ4= Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Jeff Law To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/vendors/riscv/heads/gcc-13-with-riscv-opts)] RISC-V: Fix incorrect VTYPE fusion for floating point scalar move insn[PR111037] X-Act-Checkin: gcc X-Git-Author: Juzhe-Zhong X-Git-Refname: refs/vendors/riscv/heads/gcc-13-with-riscv-opts X-Git-Oldrev: 0d795fe769e2f159ca729bfdf1870af6cebf4654 X-Git-Newrev: a3a550e4f6ae62dd21d856ce294cc1472c7c360a Message-Id: <20230821213136.027413858CD1@sourceware.org> Date: Mon, 21 Aug 2023 21:31:36 +0000 (GMT) List-Id: https://gcc.gnu.org/g:a3a550e4f6ae62dd21d856ce294cc1472c7c360a commit a3a550e4f6ae62dd21d856ce294cc1472c7c360a Author: Juzhe-Zhong Date: Thu Aug 17 13:59:06 2023 +0800 RISC-V: Fix incorrect VTYPE fusion for floating point scalar move insn[PR111037] void foo(_Float16 y, int64_t *i64p) { vint64m1_t vx =__riscv_vle64_v_i64m1 (i64p, 1); vx = __riscv_vadd_vv_i64m1 (vx, vx, 1); vfloat16m1_t vy =__riscv_vfmv_s_f_f16m1 (y, 1); asm volatile ("# use %0 %1" : : "vr"(vx), "vr" (vy)); } zve64f: foo: vsetivli zero,1,e16,mf4,ta,ma vle64.v v1,0(a0) vfmv.s.f v2,fa0 vsetvli zero,zero,e64,m1,ta,ma vadd.vv v1,v1,v1 zve64d: foo: vsetivli zero,1,e64,m1,ta,ma vle64.v v1,0(a0) vfmv.s.f v2,fa0 vadd.vv v1,v1,v1 gcc/ChangeLog: PR target/111037 * config/riscv/riscv-vsetvl.cc (float_insn_valid_sew_p): New function. (second_sew_less_than_first_sew_p): Fix bug. (first_sew_less_than_second_sew_p): Ditto. gcc/testsuite/ChangeLog: PR target/111037 * gcc.target/riscv/rvv/base/pr111037-1.c: New test. * gcc.target/riscv/rvv/base/pr111037-2.c: New test. (cherry picked from commit 29547511f7bae06f9f424f8c8583014878240016) Diff: --- gcc/config/riscv/riscv-vsetvl.cc | 22 ++++++++++++++++++++-- .../gcc.target/riscv/rvv/base/pr111037-1.c | 15 +++++++++++++++ .../gcc.target/riscv/rvv/base/pr111037-2.c | 8 ++++++++ 3 files changed, 43 insertions(+), 2 deletions(-) diff --git a/gcc/config/riscv/riscv-vsetvl.cc b/gcc/config/riscv/riscv-vsetvl.cc index 08c487d82c04..79cbac010475 100644 --- a/gcc/config/riscv/riscv-vsetvl.cc +++ b/gcc/config/riscv/riscv-vsetvl.cc @@ -1183,18 +1183,36 @@ second_ratio_invalid_for_first_lmul_p (const vector_insn_info &info1, return calculate_sew (info1.get_vlmul (), info2.get_ratio ()) == 0; } +static bool +float_insn_valid_sew_p (const vector_insn_info &info, unsigned int sew) +{ + if (info.get_insn () && info.get_insn ()->is_real () + && get_attr_type (info.get_insn ()->rtl ()) == TYPE_VFMOVFV) + { + if (sew == 16) + return TARGET_VECTOR_ELEN_FP_16; + else if (sew == 32) + return TARGET_VECTOR_ELEN_FP_32; + else if (sew == 64) + return TARGET_VECTOR_ELEN_FP_64; + } + return true; +} + static bool second_sew_less_than_first_sew_p (const vector_insn_info &info1, const vector_insn_info &info2) { - return info2.get_sew () < info1.get_sew (); + return info2.get_sew () < info1.get_sew () + || !float_insn_valid_sew_p (info1, info2.get_sew ()); } static bool first_sew_less_than_second_sew_p (const vector_insn_info &info1, const vector_insn_info &info2) { - return info1.get_sew () < info2.get_sew (); + return info1.get_sew () < info2.get_sew () + || !float_insn_valid_sew_p (info2, info1.get_sew ()); } /* return 0 if LMUL1 == LMUL2. diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111037-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111037-1.c new file mode 100644 index 000000000000..0b7b32fc3e61 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111037-1.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve64f_zvfh -mabi=ilp32d -O3" } */ + +#include "riscv_vector.h" + +void foo(_Float16 y, int64_t *i64p) +{ + vint64m1_t vx =__riscv_vle64_v_i64m1 (i64p, 1); + vx = __riscv_vadd_vv_i64m1 (vx, vx, 1); + vfloat16m1_t vy =__riscv_vfmv_s_f_f16m1 (y, 1); + asm volatile ("# use %0 %1" : : "vr"(vx), "vr" (vy)); +} + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*1,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*zero,\s*e64,\s*m1,\s*t[au],\s*m[au]} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111037-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111037-2.c new file mode 100644 index 000000000000..ac50da71726b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111037-2.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve64d_zvfh -mabi=ilp32d -O3" } */ + +#include "pr111037-1.c" + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*1,\s*e64,\s*m1,\s*t[au],\s*m[au]} 1 } } */ +/* { dg-final { scan-assembler-not {vsetvli} } } */ +/* { dg-final { scan-assembler-times {vsetivli} 1 } } */