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* [gcc r14-3613] RISC-V: Add vec_extract for BI -> QI.
@ 2023-09-01 11:00 Robin Dapp
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From: Robin Dapp @ 2023-09-01 11:00 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:ffbb19c6afc016f6dc001ad0f567d3216ff601b1
commit r14-3613-gffbb19c6afc016f6dc001ad0f567d3216ff601b1
Author: Robin Dapp <rdapp@ventanamicro.com>
Date: Thu Aug 31 09:18:00 2023 +0200
RISC-V: Add vec_extract for BI -> QI.
This patch adds a vec_extract expander that extracts a QImode from a
vector mask mode. In doing so, it helps recognize a "live
operation"/extract last idiom for mask modes. It fixes the ICE in
tree-vect-live-6.c by circumventing the fallback code in
extract_bit_field_1. The problem there is still latent, though, and
needs to be addressed separately.
gcc/ChangeLog:
* config/riscv/autovec.md (vec_extract<mode>qi): New expander.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/partial/live-2.c: New test.
* gcc.target/riscv/rvv/autovec/partial/live_run-2.c: New test.
Diff:
---
gcc/config/riscv/autovec.md | 36 +++++++++++++++
.../gcc.target/riscv/rvv/autovec/partial/live-2.c | 31 +++++++++++++
.../riscv/rvv/autovec/partial/live_run-2.c | 54 ++++++++++++++++++++++
3 files changed, 121 insertions(+)
diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
index ebe1b10aa127..2e3e8e720a52 100644
--- a/gcc/config/riscv/autovec.md
+++ b/gcc/config/riscv/autovec.md
@@ -1409,6 +1409,42 @@
DONE;
})
+;; -------------------------------------------------------------------------
+;; This extracts a bit (via QImode) from a bitmask vector.
+;; -------------------------------------------------------------------------
+(define_expand "vec_extract<mode>qi"
+ [(set (match_operand:QI 0 "register_operand")
+ (vec_select:QI
+ (match_operand:VB 1 "register_operand")
+ (parallel
+ [(match_operand 2 "nonmemory_operand")])))]
+ "TARGET_VECTOR"
+{
+ /* Create an empty byte vector and set it to one under mask. */
+ machine_mode qimode = riscv_vector::get_vector_mode
+ (QImode, GET_MODE_NUNITS (<MODE>mode)).require ();
+
+ rtx tmp1 = gen_reg_rtx (qimode);
+ emit_move_insn (tmp1, gen_const_vec_duplicate (qimode, GEN_INT (0)));
+ rtx ones = gen_const_vec_duplicate (qimode, GEN_INT (1));
+
+ rtx ops1[] = {tmp1, tmp1, ones, operands[1]};
+ riscv_vector::emit_vlmax_insn (code_for_pred_merge (qimode),
+ riscv_vector::MERGE_OP, ops1);
+
+ /* Slide down the requested byte element. */
+ rtx tmp2 = gen_reg_rtx (qimode);
+
+ rtx ops2[] = {tmp2, tmp1, operands[2]};
+ riscv_vector::emit_vlmax_insn
+ (code_for_pred_slide (UNSPEC_VSLIDEDOWN, qimode),
+ riscv_vector::BINARY_OP, ops2);
+
+ /* Extract it. */
+ emit_insn (gen_pred_extract_first (qimode, operands[0], tmp2));
+ DONE;
+})
+
;; -------------------------------------------------------------------------
;; ---- [FP] Binary operations
;; -------------------------------------------------------------------------
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/live-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/live-2.c
new file mode 100644
index 000000000000..69c2a44219ae
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/live-2.c
@@ -0,0 +1,31 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -fno-vect-cost-model --param riscv-autovec-preference=scalable -fdump-tree-optimized-details" } */
+
+#include <stdint-gcc.h>
+
+#define EXTRACT_LAST(TYPE) \
+ _Bool __attribute__ ((noipa)) \
+ test_##TYPE (TYPE *restrict x, TYPE *restrict y, int n) \
+ { \
+ _Bool last; \
+ for (int j = 0; j < n; ++j) \
+ { \
+ last = !x[j]; \
+ y[j] = last; \
+ } \
+ return last; \
+ }
+
+#define TEST_ALL(T) \
+ T (int8_t) \
+ T (int16_t) \
+ T (int32_t) \
+ T (int64_t) \
+ T (uint8_t) \
+ T (uint16_t) \
+ T (uint32_t) \
+ T (uint64_t)
+
+TEST_ALL (EXTRACT_LAST)
+
+/* { dg-final { scan-tree-dump-times "\.VEC_EXTRACT" 8 "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/live_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/live_run-2.c
new file mode 100644
index 000000000000..80d076bcf74e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/live_run-2.c
@@ -0,0 +1,54 @@
+/* { dg-do run { target { riscv_vector } } } */
+/* { dg-additional-options "--param riscv-autovec-preference=scalable" } */
+
+#include "live-2.c"
+
+#define TEST_LOOP(TYPE, N) \
+ { \
+ TYPE a##N[N]; \
+ TYPE b##N[N]; \
+ for (int i = 0; i < N; ++i) \
+ { \
+ a##N[i] = i & 1; \
+ b##N[i] = 0; \
+ asm volatile ("" ::: "memory"); \
+ } \
+ TYPE expected##N = !(a##N[N - 1]); \
+ TYPE res##N = test_##TYPE (a##N, b##N, N); \
+ if (res##N != expected##N) \
+ __builtin_abort (); \
+ for (int i = 0; i < N; ++i) \
+ { \
+ if (b##N[i] != !a##N[i]) \
+ __builtin_abort (); \
+ asm volatile ("" ::: "memory"); \
+ } \
+ }
+
+#define TEST_ALL_N(T, N) \
+ T (int8_t, N) \
+ T (int16_t, N) \
+ T (int32_t, N) \
+ T (int64_t, N) \
+ T (uint8_t, N) \
+ T (uint16_t, N) \
+ T (uint32_t, N) \
+ T (uint64_t, N)
+
+int __attribute__ ((optimize (1))) main (void)
+{
+ TEST_ALL_N (TEST_LOOP, 2);
+ TEST_ALL_N (TEST_LOOP, 3);
+ TEST_ALL_N (TEST_LOOP, 4);
+ TEST_ALL_N (TEST_LOOP, 5);
+ TEST_ALL_N (TEST_LOOP, 6);
+ TEST_ALL_N (TEST_LOOP, 7);
+ TEST_ALL_N (TEST_LOOP, 8);
+ TEST_ALL_N (TEST_LOOP, 17);
+ TEST_ALL_N (TEST_LOOP, 64);
+ TEST_ALL_N (TEST_LOOP, 107);
+ TEST_ALL_N (TEST_LOOP, 255);
+ TEST_ALL_N (TEST_LOOP, 256);
+ TEST_ALL_N (TEST_LOOP, 4389);
+ return 0;
+}
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