From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 7924) id 78A723858D33; Mon, 4 Sep 2023 07:45:44 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 78A723858D33 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1693813544; bh=/lKVp4V5RXkcfAdet2qNufaorohcRzjdY/7OU6HF/XU=; h=From:To:Subject:Date:From; b=s3UZ7PlkxjfeIzaIl9wMtqWuQoiB4sGW4kCHFvxvZo+bW/2rP6r9wTIh9R2Mo+Qpa E8njxAuXvC8u+PPqIEX5FOu9wy2Dcl5fyBy15mf3pIu8XAzSyphzuw8nJksW/ViuUG 1pUMZhL6aU6Btiu8NvVzR6ghobDqin+9ae07Tfpg= MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="utf-8" From: Pan Li To: gcc-cvs@gcc.gnu.org Subject: [gcc r14-3645] RISC-V: Support FP16 for RVV VRGATHEREI16 intrinsic X-Act-Checkin: gcc X-Git-Author: Pan Li X-Git-Refname: refs/heads/master X-Git-Oldrev: 1aceceb1e2d6e86ce183c8cc448750fa03b6f79e X-Git-Newrev: d99a868a9b100ab5a4b270a1acece60b5b6153a3 Message-Id: <20230904074544.78A723858D33@sourceware.org> Date: Mon, 4 Sep 2023 07:45:44 +0000 (GMT) List-Id: https://gcc.gnu.org/g:d99a868a9b100ab5a4b270a1acece60b5b6153a3 commit r14-3645-gd99a868a9b100ab5a4b270a1acece60b5b6153a3 Author: Pan Li Date: Mon Sep 4 15:14:28 2023 +0800 RISC-V: Support FP16 for RVV VRGATHEREI16 intrinsic This patch would like to add FP16 support for the VRGATHEREI16 intrinsic. Aka: * __riscv_vrgatherei16_vv_f16mf4 * __riscv_vrgatherei16_vv_f16mf4_m As well as f16mf2 to f16m8 types. Signed-off-by: Pan Li gcc/ChangeLog: * config/riscv/riscv-vector-builtins-types.def (vfloat16mf4_t): Add FP16 intrinsic def. (vfloat16mf2_t): Ditto. (vfloat16m1_t): Ditto. (vfloat16m2_t): Ditto. (vfloat16m4_t): Ditto. (vfloat16m8_t): Ditto. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/intrisinc-vrgatherei16.c: New test. Diff: --- gcc/config/riscv/riscv-vector-builtins-types.def | 9 +++++++ .../gcc.target/riscv/rvv/intrisinc-vrgatherei16.c | 28 ++++++++++++++++++++++ 2 files changed, 37 insertions(+) diff --git a/gcc/config/riscv/riscv-vector-builtins-types.def b/gcc/config/riscv/riscv-vector-builtins-types.def index 1c3cc0eb222d..6aa45ae9a7e5 100644 --- a/gcc/config/riscv/riscv-vector-builtins-types.def +++ b/gcc/config/riscv/riscv-vector-builtins-types.def @@ -689,11 +689,20 @@ DEF_RVV_EI16_OPS (vuint64m1_t, RVV_REQUIRE_ELEN_64) DEF_RVV_EI16_OPS (vuint64m2_t, RVV_REQUIRE_ELEN_64) DEF_RVV_EI16_OPS (vuint64m4_t, RVV_REQUIRE_ELEN_64) DEF_RVV_EI16_OPS (vuint64m8_t, RVV_REQUIRE_ELEN_64) + +DEF_RVV_EI16_OPS (vfloat16mf4_t, RVV_REQUIRE_ELEN_FP_16 | RVV_REQUIRE_MIN_VLEN_64) +DEF_RVV_EI16_OPS (vfloat16mf2_t, RVV_REQUIRE_ELEN_FP_16) +DEF_RVV_EI16_OPS (vfloat16m1_t, RVV_REQUIRE_ELEN_FP_16) +DEF_RVV_EI16_OPS (vfloat16m2_t, RVV_REQUIRE_ELEN_FP_16) +DEF_RVV_EI16_OPS (vfloat16m4_t, RVV_REQUIRE_ELEN_FP_16) +DEF_RVV_EI16_OPS (vfloat16m8_t, RVV_REQUIRE_ELEN_FP_16) + DEF_RVV_EI16_OPS (vfloat32mf2_t, RVV_REQUIRE_ELEN_FP_32 | RVV_REQUIRE_MIN_VLEN_64) DEF_RVV_EI16_OPS (vfloat32m1_t, RVV_REQUIRE_ELEN_FP_32) DEF_RVV_EI16_OPS (vfloat32m2_t, RVV_REQUIRE_ELEN_FP_32) DEF_RVV_EI16_OPS (vfloat32m4_t, RVV_REQUIRE_ELEN_FP_32) DEF_RVV_EI16_OPS (vfloat32m8_t, RVV_REQUIRE_ELEN_FP_32) + DEF_RVV_EI16_OPS (vfloat64m1_t, RVV_REQUIRE_ELEN_FP_64) DEF_RVV_EI16_OPS (vfloat64m2_t, RVV_REQUIRE_ELEN_FP_64) DEF_RVV_EI16_OPS (vfloat64m4_t, RVV_REQUIRE_ELEN_FP_64) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/intrisinc-vrgatherei16.c b/gcc/testsuite/gcc.target/riscv/rvv/intrisinc-vrgatherei16.c new file mode 100644 index 000000000000..59c6d7c887d7 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/intrisinc-vrgatherei16.c @@ -0,0 +1,28 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64 -O3 -Wno-psabi" } */ + +#include "riscv_vector.h" + +typedef _Float16 float16_t; + +vfloat16mf4_t test_vrgatherei16_vv_f16mf4(vfloat16mf4_t op1, vuint16mf4_t op2, + size_t vl) { + return __riscv_vrgatherei16_vv_f16mf4(op1, op2, vl); +} + +vfloat16m8_t test_vrgatherei16_vv_f16m8(vfloat16m8_t op1, vuint16m8_t op2, + size_t vl) { + return __riscv_vrgatherei16_vv_f16m8(op1, op2, vl); +} + +vfloat16mf4_t test_vrgatherei16_vv_f16mf4_m(vbool64_t mask, vfloat16mf4_t op1, + vuint16mf4_t op2, size_t vl) { + return __riscv_vrgatherei16_vv_f16mf4_m(mask, op1, op2, vl); +} + +vfloat16m8_t test_vrgatherei16_vv_f16m8_m(vbool2_t mask, vfloat16m8_t op1, + vuint16m8_t op2, size_t vl) { + return __riscv_vrgatherei16_vv_f16m8_m(mask, op1, op2, vl); +} + +/* { dg-final { scan-assembler-times {vrgatherei16.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 4 } } */