[gcc r14-3715] riscv: xtheadbb: Enable constant synthesis with th.srri

[Philipp Tomsich <ptomsich@gcc.gnu.org>]

https://gcc.gnu.org/g:af5cb06ec17780736749ed51cfc6dfad9397156c

commit r14-3715-gaf5cb06ec17780736749ed51cfc6dfad9397156c
Author: Christoph Müllner <christoph.muellner@vrull.eu>
Date:   Tue Sep 5 17:30:06 2023 +0200

    riscv: xtheadbb: Enable constant synthesis with th.srri
    
    Some constants can be built up using rotate-right instructions.
    The code that enables this can be found in riscv_build_integer_1().
    However, this functionality is only available for Zbb, which
    includes the rori instruction.  This patch enables this also for
    XTheadBb, which includes the th.srri instruction.
    
    Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
    
    gcc/ChangeLog:
    
            * config/riscv/riscv.cc (riscv_build_integer_1): Enable constant
            synthesis with rotate-right for XTheadBb.
    
    gcc/testsuite/ChangeLog:
    
            * gcc.target/riscv/xtheadbb-li-rotr.c: New test.

Diff:
---
 gcc/config/riscv/riscv.cc                         |  2 +-
 gcc/testsuite/gcc.target/riscv/xtheadbb-li-rotr.c | 34 +++++++++++++++++++++++
 2 files changed, 35 insertions(+), 1 deletion(-)

diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 2db9c81ac8b0..ef63079de8e1 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -566,7 +566,7 @@ riscv_build_integer_1 (struct riscv_integer_op codes[RISCV_MAX_INTEGER_OPS],
 	}
     }
 
-  if (cost > 2 && TARGET_64BIT && TARGET_ZBB)
+  if (cost > 2 && TARGET_64BIT && (TARGET_ZBB || TARGET_XTHEADBB))
     {
       int leading_ones = clz_hwi (~value);
       int trailing_ones = ctz_hwi (~value);
diff --git a/gcc/testsuite/gcc.target/riscv/xtheadbb-li-rotr.c b/gcc/testsuite/gcc.target/riscv/xtheadbb-li-rotr.c
new file mode 100644
index 000000000000..ecd50448d779
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/xtheadbb-li-rotr.c
@@ -0,0 +1,34 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_xtheadbb" } */
+
+long
+li_rori (void)
+{
+  return 0xffff77ffffffffffL;
+}
+
+long
+li_rori_2 (void)
+{
+  return 0x77ffffffffffffffL;
+}
+
+long
+li_rori_3 (void)
+{
+  return 0xfffffffeefffffffL;
+}
+
+long
+li_rori_4 (void)
+{
+  return 0x5ffffffffffffff5L;
+}
+
+long
+li_rori_5 (void)
+{
+  return 0xaffffffffffffffaL;
+}
+
+/* { dg-final { scan-assembler-times "th.srri\t" 5 } } */