[gcc(refs/vendors/riscv/heads/gcc-13-with-riscv-opts)] RISC-V: Fix incorrect nregs calculation for VLS modes

[gcc(refs/vendors/riscv/heads/gcc-13-with-riscv-opts)] RISC-V: Fix incorrect nregs calculation for VLS modes

[Jeff Law]

https://gcc.gnu.org/g:3ee4f0d4a4cd8cc9416e4672cfb38cf31a2f36f1

commit 3ee4f0d4a4cd8cc9416e4672cfb38cf31a2f36f1
Author: Juzhe-Zhong <juzhe.zhong@rivai.ai>
Date:   Fri Sep 8 15:52:03 2023 +0800

    RISC-V: Fix incorrect nregs calculation for VLS modes
    
    This patch fixes obvious bug: TARGET_MIN_VLEN is bitsize.
    
    All these following bugs are fixed with this patch:
    FAIL: gcc.target/riscv/zero-scratch-regs-3.c   -O0  (internal compiler error: in gen_reg_rtx, at emit-rtl.cc:1176)
    FAIL: gcc.target/riscv/zero-scratch-regs-3.c   -O0  (test for excess errors)
    FAIL: gcc.target/riscv/zero-scratch-regs-3.c   -O1  (internal compiler error: in gen_reg_rtx, at emit-rtl.cc:1176)
    FAIL: gcc.target/riscv/zero-scratch-regs-3.c   -O1  (test for excess errors)
    FAIL: gcc.target/riscv/zero-scratch-regs-3.c   -O2  (internal compiler error: in gen_reg_rtx, at emit-rtl.cc:1176)
    FAIL: gcc.target/riscv/zero-scratch-regs-3.c   -O2  (test for excess errors)
    FAIL: gcc.target/riscv/zero-scratch-regs-3.c   -O2 -flto -fno-use-linker-plugin -flto-partition=none  (internal compiler error: in gen_reg_rtx, at emit-rtl.cc:1176)
    FAIL: gcc.target/riscv/zero-scratch-regs-3.c   -O2 -flto -fno-use-linker-plugin -flto-partition=none  (test for excess errors)
    FAIL: gcc.target/riscv/zero-scratch-regs-3.c   -O2 -flto -fuse-linker-plugin -fno-fat-lto-objects  (internal compiler error: in gen_reg_rtx, at emit-rtl.cc:1176)
    FAIL: gcc.target/riscv/zero-scratch-regs-3.c   -O2 -flto -fuse-linker-plugin -fno-fat-lto-objects  (test for excess errors)
    FAIL: gcc.target/riscv/zero-scratch-regs-3.c   -O3 -g  (internal compiler error: in gen_reg_rtx, at emit-rtl.cc:1176)
    FAIL: gcc.target/riscv/zero-scratch-regs-3.c   -O3 -g  (test for excess errors)
    FAIL: gcc.target/riscv/zero-scratch-regs-3.c   -Os  (internal compiler error: in gen_reg_rtx, at emit-rtl.cc:1176)
    FAIL: gcc.target/riscv/zero-scratch-regs-3.c   -Os  (test for excess errors)
    FAIL: gcc.target/riscv/rvv/base/mov-13.c (internal compiler error: in partial_subreg_p, at rtl.h:3186)
    FAIL: gcc.target/riscv/rvv/base/mov-13.c (test for excess errors)
    FAIL: gcc.target/riscv/rvv/base/spill-1.c (internal compiler error: in partial_subreg_p, at rtl.h:3186)
    FAIL: gcc.target/riscv/rvv/base/spill-1.c (test for excess errors)
    FAIL: gcc.target/riscv/rvv/base/spill-2.c (internal compiler error: in partial_subreg_p, at rtl.h:3186)
    FAIL: gcc.target/riscv/rvv/base/spill-2.c (test for excess errors)
    FAIL: gcc.target/riscv/rvv/base/spill-3.c (internal compiler error: in partial_subreg_p, at rtl.h:3186)
    FAIL: gcc.target/riscv/rvv/base/spill-3.c (test for excess errors)
    FAIL: gcc.target/riscv/rvv/base/spill-4.c (internal compiler error: in partial_subreg_p, at rtl.h:3186)
    FAIL: gcc.target/riscv/rvv/base/spill-4.c (test for excess errors)
    FAIL: gcc.target/riscv/rvv/base/spill-5.c (internal compiler error: in partial_subreg_p, at rtl.h:3186)
    FAIL: gcc.target/riscv/rvv/base/spill-5.c (test for excess errors)
    FAIL: gcc.target/riscv/rvv/base/spill-6.c (internal compiler error: in partial_subreg_p, at rtl.h:3186)
    FAIL: gcc.target/riscv/rvv/base/spill-6.c (test for excess errors)
    FAIL: gcc.target/riscv/rvv/base/spill-sp-adjust.c (internal compiler error: in partial_subreg_p, at rtl.h:3186)
    FAIL: gcc.target/riscv/rvv/base/spill-sp-adjust.c (test for excess errors)
    
    gcc/ChangeLog:
    
            * config/riscv/riscv.cc (riscv_hard_regno_nregs): Fix bug.
    
    (cherry picked from commit f9cb357ae962ba2922b8507f4d96227780a063b9)

Diff:
---
 gcc/config/riscv/riscv.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index fb96493d974f..7a0f9f6465df 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -7548,7 +7548,7 @@ riscv_hard_regno_nregs (unsigned int regno, machine_mode mode)
   /* For VLS modes, we allocate registers according to TARGET_MIN_VLEN.  */
   if (riscv_v_ext_vls_mode_p (mode))
     {
-      int size = GET_MODE_SIZE (mode).to_constant ();
+      int size = GET_MODE_BITSIZE (mode).to_constant ();
       if (size < TARGET_MIN_VLEN)
 	return 1;
       else