From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 2119) id 41F013858002; Mon, 11 Sep 2023 13:38:40 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 41F013858002 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1694439520; bh=Ia6HulMj4YcCIBTVlcn9UFfgTUIHAJqYF54zvn+vYqo=; h=From:To:Subject:Date:From; b=DVA+DLus6RO0TfrUC406kblRTMSVQIY3dKm3/oztSyJoZFg+YswtHAPGnK+Isy3Do 0pb+dnsvbgxiIqIjgqOBTBzCsRiUAZaiwkzL3HkjmPdhmfyZS1ManZz2HigV9p1tQP i+UllPCa5tmqUKf9wvs0xMUsDIfmvzCuy4oz3MY8= MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain; charset="utf-8" From: Jeff Law To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/vendors/riscv/heads/gcc-13-with-riscv-opts)] riscv: thead: Fix mode attribute for extension patterns X-Act-Checkin: gcc X-Git-Author: =?utf-8?q?Christoph_M=C3=BCllner?= X-Git-Refname: refs/vendors/riscv/heads/gcc-13-with-riscv-opts X-Git-Oldrev: b775df5cec1a684e3b5d03a6314da19f784f2b53 X-Git-Newrev: 4408e05b05aa88adf0acc3f5f6bef4d21766c72a Message-Id: <20230911133840.41F013858002@sourceware.org> Date: Mon, 11 Sep 2023 13:38:40 +0000 (GMT) List-Id: https://gcc.gnu.org/g:4408e05b05aa88adf0acc3f5f6bef4d21766c72a commit 4408e05b05aa88adf0acc3f5f6bef4d21766c72a Author: Christoph Müllner Date: Fri Sep 8 08:03:23 2023 +0200 riscv: thead: Fix mode attribute for extension patterns The mode attribute of an extension pattern is usually set to the target type. Let's follow this convention consistently for xtheadbb. Signed-off-by: Christoph Müllner gcc/ChangeLog: * config/riscv/thead.md: Use more appropriate mode attributes for extensions. (cherry picked from commit 0e25761b373f075a41d43b9462366a653dbf1121) Diff: --- gcc/config/riscv/thead.md | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/gcc/config/riscv/thead.md b/gcc/config/riscv/thead.md index 29f98dec3a8a..c6bd6887f9f7 100644 --- a/gcc/config/riscv/thead.md +++ b/gcc/config/riscv/thead.md @@ -90,7 +90,7 @@ th.extu\t%0,%1,31,0 lwu\t%0,%1" [(set_attr "type" "bitmanip,load") - (set_attr "mode" "SI")]) + (set_attr "mode" "DI")]) (define_insn "*zero_extendhi2_th_extu" [(set (match_operand:GPR 0 "register_operand" "=r,r") @@ -100,7 +100,7 @@ th.extu\t%0,%1,15,0 lhu\t%0,%1" [(set_attr "type" "bitmanip,load") - (set_attr "mode" "HI")]) + (set_attr "mode" "")]) (define_insn "*th_clz2" [(set (match_operand:X 0 "register_operand" "=r")