From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 2119) id 7957A385842E; Mon, 11 Sep 2023 13:38:55 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 7957A385842E DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1694439535; bh=NSnjWMSlFRPmx5s87TfUOIDobYg/O0bi0RDGnGStoIA=; h=From:To:Subject:Date:From; b=kcka0p29JVNrsh7l3XkzHs2LhxnEnTqzY80S7VucrRUYn1yCsvtWfbc0x4E4gNefk Bg8ND2kVRaDXzkNdMqU7Z6bfpMpCCe3lwJBAX2kTqNd6c/mMKEU1vL+iCQpGY94kQk H6i8XQdrahASKaqSCzjOXlF0vX2DOEES/W5UsJAE= Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Jeff Law To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/vendors/riscv/heads/gcc-13-with-riscv-opts)] RISC-V: Fix VLS floating-point operations predicate X-Act-Checkin: gcc X-Git-Author: Juzhe-Zhong X-Git-Refname: refs/vendors/riscv/heads/gcc-13-with-riscv-opts X-Git-Oldrev: e90e0045c6ccf1fd45256633375681d9ee29967c X-Git-Newrev: de30ec6d2e010d6fe50b959fa5a88b6c3434277f Message-Id: <20230911133855.7957A385842E@sourceware.org> Date: Mon, 11 Sep 2023 13:38:55 +0000 (GMT) List-Id: https://gcc.gnu.org/g:de30ec6d2e010d6fe50b959fa5a88b6c3434277f commit de30ec6d2e010d6fe50b959fa5a88b6c3434277f Author: Juzhe-Zhong Date: Sat Sep 9 12:30:26 2023 +0800 RISC-V: Fix VLS floating-point operations predicate VLS vfadd should depend on ZVFH instead of ZVFHMIN. Obvious fix and committed. gcc/ChangeLog: * config/riscv/vector-iterators.md: Fix floating-point operations predicate. (cherry picked from commit df9a25384e6c484643b48b59b4e6e07504889b61) Diff: --- gcc/config/riscv/vector-iterators.md | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md index 7d9fcd23b498..a98ed9fcbb6f 100644 --- a/gcc/config/riscv/vector-iterators.md +++ b/gcc/config/riscv/vector-iterators.md @@ -456,18 +456,18 @@ (RVVM8DF "TARGET_VECTOR_ELEN_FP_64") (RVVM4DF "TARGET_VECTOR_ELEN_FP_64") (RVVM2DF "TARGET_VECTOR_ELEN_FP_64") (RVVM1DF "TARGET_VECTOR_ELEN_FP_64") - (V1HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16") - (V2HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16") - (V4HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16") - (V8HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16") - (V16HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16") - (V32HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 64") - (V64HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 128") - (V128HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 256") - (V256HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 512") - (V512HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 1024") - (V1024HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 2048") - (V2048HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 4096") + (V1HF "TARGET_VECTOR_VLS && TARGET_ZVFH") + (V2HF "TARGET_VECTOR_VLS && TARGET_ZVFH") + (V4HF "TARGET_VECTOR_VLS && TARGET_ZVFH") + (V8HF "TARGET_VECTOR_VLS && TARGET_ZVFH") + (V16HF "TARGET_VECTOR_VLS && TARGET_ZVFH") + (V32HF "TARGET_VECTOR_VLS && TARGET_ZVFH && TARGET_MIN_VLEN >= 64") + (V64HF "TARGET_VECTOR_VLS && TARGET_ZVFH && TARGET_MIN_VLEN >= 128") + (V128HF "TARGET_VECTOR_VLS && TARGET_ZVFH && TARGET_MIN_VLEN >= 256") + (V256HF "TARGET_VECTOR_VLS && TARGET_ZVFH && TARGET_MIN_VLEN >= 512") + (V512HF "TARGET_VECTOR_VLS && TARGET_ZVFH && TARGET_MIN_VLEN >= 1024") + (V1024HF "TARGET_VECTOR_VLS && TARGET_ZVFH && TARGET_MIN_VLEN >= 2048") + (V2048HF "TARGET_VECTOR_VLS && TARGET_ZVFH && TARGET_MIN_VLEN >= 4096") (V1SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32") (V2SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32") (V4SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32")