From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 7877) id 5D68A3858D20; Thu, 14 Sep 2023 01:06:30 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 5D68A3858D20 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1694653590; bh=8zdfiKSaWwYYcP2OzO1cy3JAuF5VJ6iISF+v1bRXbBM=; h=From:To:Subject:Date:From; b=BgQHR5BEQydq0nwdlQOuqWf7w6SZeHDyYmTYLYJhh8ehHNYZbXBXLxYfnBVKcNUbY zX4BTWICKyaDQH1R10wF0nwLNlzhxx71PRUdA/dh3LpEEamd//MHG0TMz2c88H+vdl ascm2uW7+1ECifHAFo6P0nEFhFJaBGv/ytGSzOrM= MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="utf-8" From: LuluCheng To: gcc-cvs@gcc.gnu.org Subject: [gcc r14-3974] LoongArch: Fix bug of 'di3_fake'. X-Act-Checkin: gcc X-Git-Author: Lulu Cheng X-Git-Refname: refs/heads/master X-Git-Oldrev: f9edfaf809b2935bb9aa062f9775e3b866d78468 X-Git-Newrev: 9a033b9feffc9d97d5acfe8ca3cd16359f4b714b Message-Id: <20230914010630.5D68A3858D20@sourceware.org> Date: Thu, 14 Sep 2023 01:06:30 +0000 (GMT) List-Id: https://gcc.gnu.org/g:9a033b9feffc9d97d5acfe8ca3cd16359f4b714b commit r14-3974-g9a033b9feffc9d97d5acfe8ca3cd16359f4b714b Author: Lulu Cheng Date: Mon Sep 11 16:20:29 2023 +0800 LoongArch: Fix bug of 'di3_fake'. PR target/111334 gcc/ChangeLog: * config/loongarch/loongarch.md: Fix bug of 'di3_fake'. gcc/testsuite/ChangeLog: * gcc.target/loongarch/pr111334.c: New test. Diff: --- gcc/config/loongarch/loongarch.md | 20 +++++++++----- gcc/testsuite/gcc.target/loongarch/pr111334.c | 39 +++++++++++++++++++++++++++ 2 files changed, 52 insertions(+), 7 deletions(-) diff --git a/gcc/config/loongarch/loongarch.md b/gcc/config/loongarch/loongarch.md index 1dc6b524416..4fcb6d781d5 100644 --- a/gcc/config/loongarch/loongarch.md +++ b/gcc/config/loongarch/loongarch.md @@ -72,6 +72,9 @@ UNSPEC_LUI_H_HI12 UNSPEC_TLS_LOW + ;; Fake div.w[u] mod.w[u] + UNSPEC_FAKE_ANY_DIV + UNSPEC_SIBCALL_VALUE_MULTIPLE_INTERNAL_1 UNSPEC_CALL_VALUE_MULTIPLE_INTERNAL_1 ]) @@ -900,7 +903,7 @@ (match_operand:GPR 2 "register_operand")))] "" { - if (GET_MODE (operands[0]) == SImode) + if (GET_MODE (operands[0]) == SImode && TARGET_64BIT) { rtx reg1 = gen_reg_rtx (DImode); rtx reg2 = gen_reg_rtx (DImode); @@ -920,9 +923,9 @@ }) (define_insn "*3" - [(set (match_operand:GPR 0 "register_operand" "=r,&r,&r") - (any_div:GPR (match_operand:GPR 1 "register_operand" "r,r,0") - (match_operand:GPR 2 "register_operand" "r,r,r")))] + [(set (match_operand:X 0 "register_operand" "=r,&r,&r") + (any_div:X (match_operand:X 1 "register_operand" "r,r,0") + (match_operand:X 2 "register_operand" "r,r,r")))] "" { return loongarch_output_division (".\t%0,%1,%2", operands); @@ -938,9 +941,12 @@ (define_insn "di3_fake" [(set (match_operand:DI 0 "register_operand" "=r,&r,&r") (sign_extend:DI - (any_div:SI (match_operand:DI 1 "register_operand" "r,r,0") - (match_operand:DI 2 "register_operand" "r,r,r"))))] - "" + (unspec:SI + [(subreg:SI + (any_div:DI (match_operand:DI 1 "register_operand" "r,r,0") + (match_operand:DI 2 "register_operand" "r,r,r")) 0)] + UNSPEC_FAKE_ANY_DIV)))] + "TARGET_64BIT" { return loongarch_output_division (".w\t%0,%1,%2", operands); } diff --git a/gcc/testsuite/gcc.target/loongarch/pr111334.c b/gcc/testsuite/gcc.target/loongarch/pr111334.c new file mode 100644 index 00000000000..47366afcb74 --- /dev/null +++ b/gcc/testsuite/gcc.target/loongarch/pr111334.c @@ -0,0 +1,39 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +unsigned +util_next_power_of_two (unsigned x) +{ + return (1 << __builtin_clz (x - 1)); +} + +extern int create_vec_from_array (void); + +struct ac_shader_args { + struct { + unsigned char offset; + unsigned char size; + } args[384]; +}; + +struct isel_context { + const struct ac_shader_args* args; + int arg_temps[384]; +}; + + +void +add_startpgm (struct isel_context* ctx, unsigned short arg_count) +{ + + for (unsigned i = 0, arg = 0; i < arg_count; i++) + { + unsigned size = ctx->args->args[i].size; + unsigned reg = ctx->args->args[i].offset; + + if (reg % ( 4 < util_next_power_of_two (size) + ? 4 : util_next_power_of_two (size))) + ctx->arg_temps[i] = create_vec_from_array (); + } +} +