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* [gcc r14-3997] RISC-V: Cleanup redundant reduction patterns after refactor vector mode
@ 2023-09-14 14:59 Lehua Ding
0 siblings, 0 replies; only message in thread
From: Lehua Ding @ 2023-09-14 14:59 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:14c481f7fc0a90de7e5b7aec109e12b7b5220d65
commit r14-3997-g14c481f7fc0a90de7e5b7aec109e12b7b5220d65
Author: Lehua Ding <lehua.ding@rivai.ai>
Date: Wed Sep 13 13:07:40 2023 +0800
RISC-V: Cleanup redundant reduction patterns after refactor vector mode
This patch cleanups redundant reduction patterns after Juzhe change vector mode
from fixed-size to scalable-size. For example, whether it is zvl32b, zvl64b,
zvl128b, RVVM1SI indicates that it occupies a vector register. Therefore, it is
easy to map vector modes to LMUL1 vector modes with define_mode_attr without
creating a separate pattern for each LMUL1 Mode. For example, this patch can
combine four patterns (@pred_reduc_<reduc><VQI:mode><VQI_LMUL1:mode>,
@pred_reduc_<reduc><VHI:mode><VHI_LMUL1:mode>
@pred_reduc_<reduc><VSI:mode><VSI_LMUL1:mode>,
@pred_reduc_<reduc><VDI:mode><VDI_LMUL1:mode>) to a single pattern
@pred_reduc_<reduc><mode>.
gcc/ChangeLog:
* config/riscv/riscv-v.cc (expand_reduction): Adjust call.
* config/riscv/riscv-vector-builtins-bases.cc: Adjust call.
* config/riscv/vector-iterators.md: New iterators and attrs.
* config/riscv/vector.md (@pred_reduc_<reduc><VQI:mode><VQI_LMUL1:mode>):
Removed.
(@pred_reduc_<reduc><VHI:mode><VHI_LMUL1:mode>): Removed.
(@pred_reduc_<reduc><VSI:mode><VSI_LMUL1:mode>): Removed.
(@pred_reduc_<reduc><VDI:mode><VDI_LMUL1:mode>): Removed.
(@pred_reduc_<reduc><mode>): Added.
(@pred_widen_reduc_plus<v_su><VQI:mode><VHI_LMUL1:mode>): Removed.
(@pred_widen_reduc_plus<v_su><VHI:mode><VSI_LMUL1:mode>): Removed.
(@pred_widen_reduc_plus<v_su><mode>): Added.
(@pred_widen_reduc_plus<v_su><VSI:mode><VDI_LMUL1:mode>): Removed.
(@pred_reduc_<reduc><VHF:mode><VHF_LMUL1:mode>): Removed.
(@pred_reduc_<reduc><VSF:mode><VSF_LMUL1:mode>): Removed.
(@pred_reduc_<reduc><VDF:mode><VDF_LMUL1:mode>): Removed.
(@pred_reduc_plus<order><VHF:mode><VHF_LMUL1:mode>): Removed.
(@pred_reduc_plus<order><VSF:mode><VSF_LMUL1:mode>): Removed.
(@pred_reduc_plus<order><mode>): Added.
(@pred_reduc_plus<order><VDF:mode><VDF_LMUL1:mode>): Removed.
(@pred_widen_reduc_plus<order><VHF:mode><VSF_LMUL1:mode>): Removed.
(@pred_widen_reduc_plus<order><VSF:mode><VDF_LMUL1:mode>): Removed.
(@pred_widen_reduc_plus<order><mode>): Added.
Diff:
---
gcc/config/riscv/riscv-v.cc | 4 +-
gcc/config/riscv/riscv-vector-builtins-bases.cc | 15 +-
gcc/config/riscv/vector-iterators.md | 47 +--
gcc/config/riscv/vector.md | 369 +++++-------------------
4 files changed, 101 insertions(+), 334 deletions(-)
diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index 76e6094f45b..68b36d9dc4f 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -3230,7 +3230,7 @@ expand_reduction (rtx_code code, rtx *ops, rtx init, reduction_type type)
= code_for_pred_reduc_plus (type == reduction_type::UNORDERED
? UNSPEC_UNORDERED
: UNSPEC_ORDERED,
- vmode, m1_mode);
+ vmode);
if (type == reduction_type::MASK_LEN_FOLD_LEFT)
{
rtx mask = ops[3];
@@ -3243,7 +3243,7 @@ expand_reduction (rtx_code code, rtx *ops, rtx init, reduction_type type)
}
else
{
- insn_code icode = code_for_pred_reduc (code, vmode, m1_mode);
+ insn_code icode = code_for_pred_reduc (code, vmode);
emit_vlmax_insn (icode, REDUCE_OP, reduc_ops);
}
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc b/gcc/config/riscv/riscv-vector-builtins-bases.cc
index ee218a03017..c54ea6f0560 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
@@ -1541,8 +1541,7 @@ public:
rtx expand (function_expander &e) const override
{
- return e.use_exact_insn (
- code_for_pred_reduc (CODE, e.vector_mode (), e.ret_mode ()));
+ return e.use_exact_insn (code_for_pred_reduc (CODE, e.vector_mode ()));
}
};
@@ -1555,9 +1554,8 @@ public:
rtx expand (function_expander &e) const override
{
- return e.use_exact_insn (code_for_pred_widen_reduc_plus (UNSPEC,
- e.vector_mode (),
- e.ret_mode ()));
+ return e.use_exact_insn (
+ code_for_pred_widen_reduc_plus (UNSPEC, e.vector_mode ()));
}
};
@@ -1576,7 +1574,7 @@ public:
rtx expand (function_expander &e) const override
{
return e.use_exact_insn (
- code_for_pred_reduc_plus (UNSPEC, e.vector_mode (), e.ret_mode ()));
+ code_for_pred_reduc_plus (UNSPEC, e.vector_mode ()));
}
};
@@ -1594,9 +1592,8 @@ public:
rtx expand (function_expander &e) const override
{
- return e.use_exact_insn (code_for_pred_widen_reduc_plus (UNSPEC,
- e.vector_mode (),
- e.ret_mode ()));
+ return e.use_exact_insn (
+ code_for_pred_widen_reduc_plus (UNSPEC, e.vector_mode ()));
}
};
diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md
index e70a9bc5c74..deb89cbcedc 100644
--- a/gcc/config/riscv/vector-iterators.md
+++ b/gcc/config/riscv/vector-iterators.md
@@ -671,6 +671,15 @@
RVVM8SI RVVM4SI RVVM2SI RVVM1SI (RVVMF2SI "TARGET_MIN_VLEN > 32")
])
+(define_mode_iterator VF_HS [
+ (RVVM8HF "TARGET_ZVFH") (RVVM4HF "TARGET_ZVFH") (RVVM2HF "TARGET_ZVFH")
+ (RVVM1HF "TARGET_ZVFH") (RVVMF2HF "TARGET_ZVFH")
+ (RVVMF4HF "TARGET_ZVFH && TARGET_MIN_VLEN > 32")
+
+ (RVVM8SF "TARGET_VECTOR_ELEN_FP_32") (RVVM4SF "TARGET_VECTOR_ELEN_FP_32") (RVVM2SF "TARGET_VECTOR_ELEN_FP_32")
+ (RVVM1SF "TARGET_VECTOR_ELEN_FP_32") (RVVMF2SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32")
+])
+
(define_mode_iterator V_VLSI_QHS [
RVVM8QI RVVM4QI RVVM2QI RVVM1QI RVVMF2QI RVVMF4QI (RVVMF8QI "TARGET_MIN_VLEN > 32")
@@ -1237,32 +1246,32 @@
(RVVM2DF "TARGET_VECTOR_ELEN_FP_64") (RVVM1DF "TARGET_VECTOR_ELEN_FP_64")
])
-(define_mode_iterator VQI_LMUL1 [
- RVVM1QI
-])
+(define_mode_attr V_LMUL1 [
+ (RVVM8QI "RVVM1QI") (RVVM4QI "RVVM1QI") (RVVM2QI "RVVM1QI") (RVVM1QI "RVVM1QI") (RVVMF2QI "RVVM1QI") (RVVMF4QI "RVVM1QI") (RVVMF8QI "RVVM1QI")
-(define_mode_iterator VHI_LMUL1 [
- RVVM1HI
-])
+ (RVVM8HI "RVVM1HI") (RVVM4HI "RVVM1HI") (RVVM2HI "RVVM1HI") (RVVM1HI "RVVM1HI") (RVVMF2HI "RVVM1HI") (RVVMF4HI "RVVM1HI")
-(define_mode_iterator VSI_LMUL1 [
- RVVM1SI
-])
+ (RVVM8SI "RVVM1SI") (RVVM4SI "RVVM1SI") (RVVM2SI "RVVM1SI") (RVVM1SI "RVVM1SI") (RVVMF2SI "RVVM1SI")
-(define_mode_iterator VDI_LMUL1 [
- (RVVM1DI "TARGET_VECTOR_ELEN_64")
-])
+ (RVVM8DI "RVVM1DI") (RVVM4DI "RVVM1DI") (RVVM2DI "RVVM1DI") (RVVM1DI "RVVM1DI")
-(define_mode_iterator VHF_LMUL1 [
- (RVVM1HF "TARGET_ZVFH")
-])
+ (RVVM8HF "RVVM1HF") (RVVM4HF "RVVM1HF") (RVVM2HF "RVVM1HF") (RVVM1HF "RVVM1HF") (RVVMF2HF "RVVM1HF") (RVVMF4HF "RVVM1HF")
-(define_mode_iterator VSF_LMUL1 [
- (RVVM1SF "TARGET_VECTOR_ELEN_FP_32")
+ (RVVM8SF "RVVM1SF") (RVVM4SF "RVVM1SF") (RVVM2SF "RVVM1SF") (RVVM1SF "RVVM1SF") (RVVMF2SF "RVVM1SF")
+
+ (RVVM8DF "RVVM1DF") (RVVM4DF "RVVM1DF") (RVVM2DF "RVVM1DF") (RVVM1DF "RVVM1DF")
])
-(define_mode_iterator VDF_LMUL1 [
- (RVVM1DF "TARGET_VECTOR_ELEN_FP_64")
+(define_mode_attr V_EXT_LMUL1 [
+ (RVVM8QI "RVVM1HI") (RVVM4QI "RVVM1HI") (RVVM2QI "RVVM1HI") (RVVM1QI "RVVM1HI") (RVVMF2QI "RVVM1HI") (RVVMF4QI "RVVM1HI") (RVVMF8QI "RVVM1HI")
+
+ (RVVM8HI "RVVM1SI") (RVVM4HI "RVVM1SI") (RVVM2HI "RVVM1SI") (RVVM1HI "RVVM1SI") (RVVMF2HI "RVVM1SI") (RVVMF4HI "RVVM1SI")
+
+ (RVVM8SI "RVVM1DI") (RVVM4SI "RVVM1DI") (RVVM2SI "RVVM1DI") (RVVM1SI "RVVM1DI") (RVVMF2SI "RVVM1DI")
+
+ (RVVM8HF "RVVM1SF") (RVVM4HF "RVVM1SF") (RVVM2HF "RVVM1SF") (RVVM1HF "RVVM1SF") (RVVMF2HF "RVVM1SF") (RVVMF4HF "RVVM1SF")
+
+ (RVVM8SF "RVVM1DF") (RVVM4SF "RVVM1DF") (RVVM2SF "RVVM1DF") (RVVM1SF "RVVM1DF") (RVVMF2SF "RVVM1DF")
])
(define_mode_attr VINDEX [
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index 8c0e86576a0..5b1ec36816a 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -7725,265 +7725,78 @@
;; - 14.4 Vector Widening Floating-Point Reduction Instructions
;; -------------------------------------------------------------------------------
-;; For reduction operations, we should have seperate patterns for
-;; different types. For each type, we will cover MIN_VLEN == 32, MIN_VLEN == 64
-;; and the MIN_VLEN >= 128 from the well defined iterators.
-;; Since reduction need LMUL = 1 scalar operand as the input operand
-;; and they are different.
-
-;; Integer Reduction for QI
-(define_insn "@pred_reduc_<reduc><VQI:mode><VQI_LMUL1:mode>"
- [(set (match_operand:VQI_LMUL1 0 "register_operand" "=vr, vr")
- (unspec:VQI_LMUL1
- [(unspec:<VQI:VM>
- [(match_operand:<VQI:VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
- (match_operand 5 "vector_length_operand" " rK, rK")
- (match_operand 6 "const_int_operand" " i, i")
- (match_operand 7 "const_int_operand" " i, i")
- (reg:SI VL_REGNUM)
- (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
- (any_reduc:VQI
- (vec_duplicate:VQI
- (vec_select:<VEL>
- (match_operand:VQI_LMUL1 4 "register_operand" " vr, vr")
- (parallel [(const_int 0)])))
- (match_operand:VQI 3 "register_operand" " vr, vr"))
- (match_operand:VQI_LMUL1 2 "vector_merge_operand" " vu, 0")] UNSPEC_REDUC))]
- "TARGET_VECTOR"
- "vred<reduc>.vs\t%0,%3,%4%p1"
- [(set_attr "type" "vired")
- (set_attr "mode" "<VQI:MODE>")])
-
-;; Integer Reduction for HI
-(define_insn "@pred_reduc_<reduc><VHI:mode><VHI_LMUL1:mode>"
- [(set (match_operand:VHI_LMUL1 0 "register_operand" "=vr, vr")
- (unspec:VHI_LMUL1
- [(unspec:<VHI:VM>
- [(match_operand:<VHI:VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
- (match_operand 5 "vector_length_operand" " rK, rK")
- (match_operand 6 "const_int_operand" " i, i")
- (match_operand 7 "const_int_operand" " i, i")
- (reg:SI VL_REGNUM)
- (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
- (any_reduc:VHI
- (vec_duplicate:VHI
- (vec_select:<VEL>
- (match_operand:VHI_LMUL1 4 "register_operand" " vr, vr")
- (parallel [(const_int 0)])))
- (match_operand:VHI 3 "register_operand" " vr, vr"))
- (match_operand:VHI_LMUL1 2 "vector_merge_operand" " vu, 0")] UNSPEC_REDUC))]
- "TARGET_VECTOR"
- "vred<reduc>.vs\t%0,%3,%4%p1"
- [(set_attr "type" "vired")
- (set_attr "mode" "<VHI:MODE>")])
-
-;; Integer Reduction for SI
-(define_insn "@pred_reduc_<reduc><VSI:mode><VSI_LMUL1:mode>"
- [(set (match_operand:VSI_LMUL1 0 "register_operand" "=vr, vr")
- (unspec:VSI_LMUL1
- [(unspec:<VSI:VM>
- [(match_operand:<VSI:VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
- (match_operand 5 "vector_length_operand" " rK, rK")
- (match_operand 6 "const_int_operand" " i, i")
- (match_operand 7 "const_int_operand" " i, i")
- (reg:SI VL_REGNUM)
- (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
- (any_reduc:VSI
- (vec_duplicate:VSI
- (vec_select:<VEL>
- (match_operand:VSI_LMUL1 4 "register_operand" " vr, vr")
- (parallel [(const_int 0)])))
- (match_operand:VSI 3 "register_operand" " vr, vr"))
- (match_operand:VSI_LMUL1 2 "vector_merge_operand" " vu, 0")] UNSPEC_REDUC))]
- "TARGET_VECTOR"
- "vred<reduc>.vs\t%0,%3,%4%p1"
- [(set_attr "type" "vired")
- (set_attr "mode" "<VSI:MODE>")])
-
-;; Integer Reduction for DI
-(define_insn "@pred_reduc_<reduc><VDI:mode><VDI_LMUL1:mode>"
- [(set (match_operand:VDI_LMUL1 0 "register_operand" "=vr, vr")
- (unspec:VDI_LMUL1
- [(unspec:<VDI:VM>
- [(match_operand:<VDI:VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
+;; Integer Reduction (vred(sum|maxu|max|minu|min|and|or|xor).vs)
+(define_insn "@pred_reduc_<reduc><mode>"
+ [(set (match_operand:<V_LMUL1> 0 "register_operand" "=vr, vr")
+ (unspec:<V_LMUL1>
+ [(unspec:<VM>
+ [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
(match_operand 5 "vector_length_operand" " rK, rK")
(match_operand 6 "const_int_operand" " i, i")
(match_operand 7 "const_int_operand" " i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
- (any_reduc:VDI
- (vec_duplicate:VDI
+ (any_reduc:VI
+ (vec_duplicate:VI
(vec_select:<VEL>
- (match_operand:VDI_LMUL1 4 "register_operand" " vr, vr")
+ (match_operand:<V_LMUL1> 4 "register_operand" " vr, vr")
(parallel [(const_int 0)])))
- (match_operand:VDI 3 "register_operand" " vr, vr"))
- (match_operand:VDI_LMUL1 2 "vector_merge_operand" " vu, 0")] UNSPEC_REDUC))]
+ (match_operand:VI 3 "register_operand" " vr, vr"))
+ (match_operand:<V_LMUL1> 2 "vector_merge_operand" " vu, 0")] UNSPEC_REDUC))]
"TARGET_VECTOR"
"vred<reduc>.vs\t%0,%3,%4%p1"
[(set_attr "type" "vired")
- (set_attr "mode" "<VDI:MODE>")])
-
-;; Integer Reduction Widen for QI, HI = QI op HI
-(define_insn "@pred_widen_reduc_plus<v_su><VQI:mode><VHI_LMUL1:mode>"
- [(set (match_operand:VHI_LMUL1 0 "register_operand" "=&vr,&vr")
- (unspec:VHI_LMUL1
- [(unspec:<VQI:VM>
- [(match_operand:<VQI:VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
- (match_operand 5 "vector_length_operand" " rK, rK")
- (match_operand 6 "const_int_operand" " i, i")
- (match_operand 7 "const_int_operand" " i, i")
- (reg:SI VL_REGNUM)
- (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
- (match_operand:VQI 3 "register_operand" " vr, vr")
- (match_operand:VHI_LMUL1 4 "register_operand" " vr, vr")
- (match_operand:VHI_LMUL1 2 "vector_merge_operand" " vu, 0")] WREDUC))]
- "TARGET_VECTOR"
- "vwredsum<v_su>.vs\t%0,%3,%4%p1"
- [(set_attr "type" "viwred")
- (set_attr "mode" "<VQI:MODE>")])
+ (set_attr "mode" "<MODE>")])
-;; Integer Reduction Widen for HI, SI = HI op SI
-(define_insn "@pred_widen_reduc_plus<v_su><VHI:mode><VSI_LMUL1:mode>"
- [(set (match_operand:VSI_LMUL1 0 "register_operand" "=&vr,&vr")
- (unspec:VSI_LMUL1
- [(unspec:<VHI:VM>
- [(match_operand:<VHI:VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
- (match_operand 5 "vector_length_operand" " rK, rK")
- (match_operand 6 "const_int_operand" " i, i")
- (match_operand 7 "const_int_operand" " i, i")
+;; Integer Reduction Sum Widen (vwredsum[u].vs)
+(define_insn "@pred_widen_reduc_plus<v_su><mode>"
+ [(set (match_operand:<V_EXT_LMUL1> 0 "register_operand" "=&vr,&vr")
+ (unspec:<V_EXT_LMUL1>
+ [(unspec:<VM>
+ [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
+ (match_operand 5 "vector_length_operand" " rK, rK")
+ (match_operand 6 "const_int_operand" " i, i")
+ (match_operand 7 "const_int_operand" " i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
- (match_operand:VHI 3 "register_operand" " vr, vr")
- (match_operand:VSI_LMUL1 4 "register_operand" " vr, vr")
- (match_operand:VSI_LMUL1 2 "vector_merge_operand" " vu, 0")] WREDUC))]
+ (match_operand:VI_QHS 3 "register_operand" " vr, vr")
+ (match_operand:<V_EXT_LMUL1> 4 "register_operand" " vr, vr")
+ (match_operand:<V_EXT_LMUL1> 2 "vector_merge_operand" " vu, 0")] WREDUC))]
"TARGET_VECTOR"
"vwredsum<v_su>.vs\t%0,%3,%4%p1"
[(set_attr "type" "viwred")
- (set_attr "mode" "<VHI:MODE>")])
+ (set_attr "mode" "<MODE>")])
-;; Integer Reduction Widen for SI, DI = SI op DI
-(define_insn "@pred_widen_reduc_plus<v_su><VSI:mode><VDI_LMUL1:mode>"
- [(set (match_operand:VDI_LMUL1 0 "register_operand" "=&vr,&vr")
- (unspec:VDI_LMUL1
- [(unspec:<VSI:VM>
- [(match_operand:<VSI:VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
- (match_operand 5 "vector_length_operand" " rK, rK")
- (match_operand 6 "const_int_operand" " i, i")
- (match_operand 7 "const_int_operand" " i, i")
- (reg:SI VL_REGNUM)
- (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
- (match_operand:VSI 3 "register_operand" " vr, vr")
- (match_operand:VDI_LMUL1 4 "register_operand" " vr, vr")
- (match_operand:VDI_LMUL1 2 "vector_merge_operand" " vu, 0")] WREDUC))]
- "TARGET_VECTOR"
- "vwredsum<v_su>.vs\t%0,%3,%4%p1"
- [(set_attr "type" "viwred")
- (set_attr "mode" "<VSI:MODE>")])
-
-;; Float Reduction for HF
-(define_insn "@pred_reduc_<reduc><VHF:mode><VHF_LMUL1:mode>"
- [(set (match_operand:VHF_LMUL1 0 "register_operand" "=vr, vr")
- (unspec:VHF_LMUL1
- [(unspec:<VHF:VM>
- [(match_operand:<VHF:VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
- (match_operand 5 "vector_length_operand" " rK, rK")
- (match_operand 6 "const_int_operand" " i, i")
- (match_operand 7 "const_int_operand" " i, i")
- (reg:SI VL_REGNUM)
- (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
- (any_reduc:VHF
- (vec_duplicate:VHF
- (vec_select:<VEL>
- (match_operand:VHF_LMUL1 4 "register_operand" " vr, vr")
- (parallel [(const_int 0)])))
- (match_operand:VHF 3 "register_operand" " vr, vr"))
- (match_operand:VHF_LMUL1 2 "vector_merge_operand" " vu, 0")] UNSPEC_REDUC))]
- "TARGET_VECTOR"
- "vfred<reduc>.vs\t%0,%3,%4%p1"
- [(set_attr "type" "vfredu")
- (set_attr "mode" "<VHF:MODE>")])
-
-;; Float Reduction for SF
-(define_insn "@pred_reduc_<reduc><VSF:mode><VSF_LMUL1:mode>"
- [(set (match_operand:VSF_LMUL1 0 "register_operand" "=vr, vr")
- (unspec:VSF_LMUL1
- [(unspec:<VSF:VM>
- [(match_operand:<VSF:VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
- (match_operand 5 "vector_length_operand" " rK, rK")
- (match_operand 6 "const_int_operand" " i, i")
- (match_operand 7 "const_int_operand" " i, i")
- (reg:SI VL_REGNUM)
- (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
- (any_reduc:VSF
- (vec_duplicate:VSF
- (vec_select:<VEL>
- (match_operand:VSF_LMUL1 4 "register_operand" " vr, vr")
- (parallel [(const_int 0)])))
- (match_operand:VSF 3 "register_operand" " vr, vr"))
- (match_operand:VSF_LMUL1 2 "vector_merge_operand" " vu, 0")] UNSPEC_REDUC))]
- "TARGET_VECTOR"
- "vfred<reduc>.vs\t%0,%3,%4%p1"
- [(set_attr "type" "vfredu")
- (set_attr "mode" "<VSF:MODE>")])
-
-;; Float Reduction for DF
-(define_insn "@pred_reduc_<reduc><VDF:mode><VDF_LMUL1:mode>"
- [(set (match_operand:VDF_LMUL1 0 "register_operand" "=vr, vr")
- (unspec:VDF_LMUL1
- [(unspec:<VDF:VM>
- [(match_operand:<VDF:VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
+;; Float Reduction (vfred(max|min).vs)
+(define_insn "@pred_reduc_<reduc><mode>"
+ [(set (match_operand:<V_LMUL1> 0 "register_operand" "=vr, vr")
+ (unspec:<V_LMUL1>
+ [(unspec:<VM>
+ [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
(match_operand 5 "vector_length_operand" " rK, rK")
(match_operand 6 "const_int_operand" " i, i")
(match_operand 7 "const_int_operand" " i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
- (any_reduc:VDF
- (vec_duplicate:VDF
+ (any_freduc:VF
+ (vec_duplicate:VF
(vec_select:<VEL>
- (match_operand:VDF_LMUL1 4 "register_operand" " vr, vr")
+ (match_operand:<V_LMUL1> 4 "register_operand" " vr, vr")
(parallel [(const_int 0)])))
- (match_operand:VDF 3 "register_operand" " vr, vr"))
- (match_operand:VDF_LMUL1 2 "vector_merge_operand" " vu, 0")] UNSPEC_REDUC))]
+ (match_operand:VF 3 "register_operand" " vr, vr"))
+ (match_operand:<V_LMUL1> 2 "vector_merge_operand" " vu, 0")] UNSPEC_REDUC))]
"TARGET_VECTOR"
"vfred<reduc>.vs\t%0,%3,%4%p1"
[(set_attr "type" "vfredu")
- (set_attr "mode" "<VDF:MODE>")])
-
-;; Float Ordered Reduction Sum for HF
-(define_insn "@pred_reduc_plus<order><VHF:mode><VHF_LMUL1:mode>"
- [(set (match_operand:VHF_LMUL1 0 "register_operand" "=vr,vr")
- (unspec:VHF_LMUL1
- [(unspec:VHF_LMUL1
- [(unspec:<VHF:VM>
- [(match_operand:<VHF:VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
- (match_operand 5 "vector_length_operand" " rK, rK")
- (match_operand 6 "const_int_operand" " i, i")
- (match_operand 7 "const_int_operand" " i, i")
- (match_operand 8 "const_int_operand" " i, i")
- (reg:SI VL_REGNUM)
- (reg:SI VTYPE_REGNUM)
- (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
- (plus:VHF
- (vec_duplicate:VHF
- (vec_select:<VEL>
- (match_operand:VHF_LMUL1 4 "register_operand" " vr, vr")
- (parallel [(const_int 0)])))
- (match_operand:VHF 3 "register_operand" " vr, vr"))
- (match_operand:VHF_LMUL1 2 "vector_merge_operand" " vu, 0")] UNSPEC_REDUC)] ORDER))]
- "TARGET_VECTOR"
- "vfred<order>sum.vs\t%0,%3,%4%p1"
- [(set_attr "type" "vfred<order>")
- (set_attr "mode" "<VHF:MODE>")
- (set (attr "frm_mode")
- (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))])
+ (set_attr "mode" "<MODE>")])
-;; Float Ordered Reduction Sum for SF
-(define_insn "@pred_reduc_plus<order><VSF:mode><VSF_LMUL1:mode>"
- [(set (match_operand:VSF_LMUL1 0 "register_operand" "=vr,vr")
- (unspec:VSF_LMUL1
- [(unspec:VSF_LMUL1
- [(unspec:<VSF:VM>
- [(match_operand:<VSF:VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
+;; Float Ordered Reduction Sum (vfred[ou]sum.vs)
+(define_insn "@pred_reduc_plus<order><mode>"
+ [(set (match_operand:<V_LMUL1> 0 "register_operand" "=vr,vr")
+ (unspec:<V_LMUL1>
+ [(unspec:<V_LMUL1>
+ [(unspec:<VM>
+ [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
(match_operand 5 "vector_length_operand" " rK, rK")
(match_operand 6 "const_int_operand" " i, i")
(match_operand 7 "const_int_operand" " i, i")
@@ -7991,93 +7804,41 @@
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)
(reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
- (plus:VSF
- (vec_duplicate:VSF
+ (plus:VF
+ (vec_duplicate:VF
(vec_select:<VEL>
- (match_operand:VSF_LMUL1 4 "register_operand" " vr, vr")
+ (match_operand:<V_LMUL1> 4 "register_operand" " vr, vr")
(parallel [(const_int 0)])))
- (match_operand:VSF 3 "register_operand" " vr, vr"))
- (match_operand:VSF_LMUL1 2 "vector_merge_operand" " vu, 0")] UNSPEC_REDUC)] ORDER))]
+ (match_operand:VF 3 "register_operand" " vr, vr"))
+ (match_operand:<V_LMUL1> 2 "vector_merge_operand" " vu, 0")] UNSPEC_REDUC)] ORDER))]
"TARGET_VECTOR"
"vfred<order>sum.vs\t%0,%3,%4%p1"
[(set_attr "type" "vfred<order>")
- (set_attr "mode" "<VSF:MODE>")
- (set (attr "frm_mode")
- (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))])
-
-;; Float Ordered Reduction Sum for DF
-(define_insn "@pred_reduc_plus<order><VDF:mode><VDF_LMUL1:mode>"
- [(set (match_operand:VDF_LMUL1 0 "register_operand" "=vr,vr")
- (unspec:VDF_LMUL1
- [(unspec:VDF_LMUL1
- [(unspec:<VDF:VM>
- [(match_operand:<VDF:VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
- (match_operand 5 "vector_length_operand" " rK, rK")
- (match_operand 6 "const_int_operand" " i, i")
- (match_operand 7 "const_int_operand" " i, i")
- (match_operand 8 "const_int_operand" " i, i")
- (reg:SI VL_REGNUM)
- (reg:SI VTYPE_REGNUM)
- (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
- (plus:VDF
- (vec_duplicate:VDF
- (vec_select:<VEL>
- (match_operand:VDF_LMUL1 4 "register_operand" " vr, vr")
- (parallel [(const_int 0)])))
- (match_operand:VDF 3 "register_operand" " vr, vr"))
- (match_operand:VDF_LMUL1 2 "vector_merge_operand" " vu, 0")] UNSPEC_REDUC)] ORDER))]
- "TARGET_VECTOR"
- "vfred<order>sum.vs\t%0,%3,%4%p1"
- [(set_attr "type" "vfred<order>")
- (set_attr "mode" "<VDF:MODE>")
- (set (attr "frm_mode")
- (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))])
-
-;; Float Widen Reduction for HF, aka SF = HF op SF
-(define_insn "@pred_widen_reduc_plus<order><VHF:mode><VSF_LMUL1:mode>"
- [(set (match_operand:VSF_LMUL1 0 "register_operand" "=&vr, &vr")
- (unspec:VSF_LMUL1
- [(unspec:VSF_LMUL1
- [(unspec:<VHF:VM>
- [(match_operand:<VHF:VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
- (match_operand 5 "vector_length_operand" " rK, rK")
- (match_operand 6 "const_int_operand" " i, i")
- (match_operand 7 "const_int_operand" " i, i")
- (match_operand 8 "const_int_operand" " i, i")
- (reg:SI VL_REGNUM)
- (reg:SI VTYPE_REGNUM)
- (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
- (match_operand:VHF 3 "register_operand" " vr, vr")
- (match_operand:VSF_LMUL1 4 "register_operand" " vr, vr")
- (match_operand:VSF_LMUL1 2 "vector_merge_operand" " vu, 0")] UNSPEC_WREDUC_SUM)] ORDER))]
- "TARGET_VECTOR"
- "vfwred<order>sum.vs\t%0,%3,%4%p1"
- [(set_attr "type" "vfwred<order>")
- (set_attr "mode" "<VHF:MODE>")
+ (set_attr "mode" "<MODE>")
(set (attr "frm_mode")
(symbol_ref "riscv_vector::get_frm_mode (operands[8])"))])
-;; Float Widen Reduction for SF, aka DF = SF * DF
-(define_insn "@pred_widen_reduc_plus<order><VSF:mode><VDF_LMUL1:mode>"
- [(set (match_operand:VDF_LMUL1 0 "register_operand" "=&vr, &vr")
- (unspec:VDF_LMUL1
- [(unspec:VDF_LMUL1
- [(unspec:<VSF:VM>
- [(match_operand:<VSF:VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
- (match_operand 5 "vector_length_operand" " rK, rK")
- (match_operand 6 "const_int_operand" " i, i")
- (match_operand 7 "const_int_operand" " i, i")
- (match_operand 8 "const_int_operand" " i, i")
+;; Float Widen Reduction Sum (vfwred[ou]sum.vs)
+(define_insn "@pred_widen_reduc_plus<order><mode>"
+ [(set (match_operand:<V_EXT_LMUL1> 0 "register_operand" "=&vr, &vr")
+ (unspec:<V_EXT_LMUL1>
+ [(unspec:<V_EXT_LMUL1>
+ [(unspec:<VM>
+ [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
+ (match_operand 5 "vector_length_operand" " rK, rK")
+ (match_operand 6 "const_int_operand" " i, i")
+ (match_operand 7 "const_int_operand" " i, i")
+ (match_operand 8 "const_int_operand" " i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)
(reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
- (match_operand:VSF 3 "register_operand" " vr, vr")
- (match_operand:VDF_LMUL1 4 "register_operand" " vr, vr")
- (match_operand:VDF_LMUL1 2 "vector_merge_operand" " vu, 0")] UNSPEC_WREDUC_SUM)] ORDER))]
+ (match_operand:VF_HS 3 "register_operand" " vr, vr")
+ (match_operand:<V_EXT_LMUL1> 4 "register_operand" " vr, vr")
+ (match_operand:<V_EXT_LMUL1> 2 "vector_merge_operand" " vu, 0")] UNSPEC_WREDUC_SUM)] ORDER))]
"TARGET_VECTOR"
"vfwred<order>sum.vs\t%0,%3,%4%p1"
[(set_attr "type" "vfwred<order>")
- (set_attr "mode" "<VSF:MODE>")
+ (set_attr "mode" "<MODE>")
(set (attr "frm_mode")
(symbol_ref "riscv_vector::get_frm_mode (operands[8])"))])
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2023-09-14 14:59 [gcc r14-3997] RISC-V: Cleanup redundant reduction patterns after refactor vector mode Lehua Ding
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