[gcc(refs/users/meissner/heads/work134)] Add -mno-lxvp and -mno-stxvp.

[gcc(refs/users/meissner/heads/work134)] Add -mno-lxvp and -mno-stxvp.

[Michael Meissner]

https://gcc.gnu.org/g:d3cc619be917e045d9211c312b19adf12f8e01dd

commit d3cc619be917e045d9211c312b19adf12f8e01dd
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Fri Sep 15 13:34:48 2023 -0400

    Add -mno-lxvp and -mno-stxvp.
    
    This patch adds the options -mno-lxvp and -mno-stxvp that control whether GCC
    will generate vector pair load/stores or split the instructions into separate
    vector loads/stores.  These switches are not documented, but are there to allow
    us to look at some places where the paired load/store instructions slow things
    down.
    
    With this patch, GCC will not allow X-form (register + register) vector
    pair loads or stores unless both lxvp and stxvp are being generated.
    
    I also added the lxvp and stxvp command line options to the options that the
    user can enable or disable with #pragma target or attribute target.
    
    The default is to generate the vector pair load/store instructions.
    
    2023-09-15  Michael Meissner  <meissner@linux.ibm.com>
    
    gcc/
    
            * config/rs6000/mma.md (movoo): Add support for -mno-lxvp and
            -mno-stxvp.
            * config/rs6000/rs6000.cc (rs6000_debug_reg_global): If -mdebug=reg,
            print out whether we are generating lxvp and/or stxvp instructions.
            (rs6000_option_override_internal): Warn if -mlxvp or -mstxvp was used
            without -mmma being set.
            (rs6000_setup_reg_addr_masks structure): Add support for -mno-lxvp and
            -mno-stxvp.
            (rs6000_opt_vars): Add lxvp and stxvp command line options.
            * config/rs6000/rs6000.md (isa attribute): Add lxvp and stxvp isa
            support.
            (enabled attribute): Likewise.
            * config/rs6000/rs6000.opt (-mlxvp): New option.
            (-mstxvp): Likewise.
    
    gcc/testsuite/
    
            * gcc.target/powerpc/p10-lxvp-stxvp.c: New test.

Diff:
---
 gcc/config/rs6000/mma.md                          | 15 ++++--
 gcc/config/rs6000/rs6000.cc                       | 30 +++++++++++-
 gcc/config/rs6000/rs6000.md                       | 10 +++-
 gcc/config/rs6000/rs6000.opt                      |  8 ++++
 gcc/testsuite/gcc.target/powerpc/p10-lxvp-stxvp.c | 56 +++++++++++++++++++++++
 5 files changed, 111 insertions(+), 8 deletions(-)

diff --git a/gcc/config/rs6000/mma.md b/gcc/config/rs6000/mma.md
index 575751d477e..70ba5b70c1b 100644
--- a/gcc/config/rs6000/mma.md
+++ b/gcc/config/rs6000/mma.md
@@ -293,25 +293,30 @@
 })
 
 (define_insn_and_split "*movoo"
-  [(set (match_operand:OO 0 "nonimmediate_operand" "=wa,ZwO,wa")
-	(match_operand:OO 1 "input_operand" "ZwO,wa,wa"))]
+  [(set (match_operand:OO 0 "nonimmediate_operand" "=wa,wa,ZwO,QwO,wa")
+	(match_operand:OO 1 "input_operand" "ZwO,QwO,wa,wa,wa"))]
   "TARGET_MMA
    && (gpc_reg_operand (operands[0], OOmode)
        || gpc_reg_operand (operands[1], OOmode))"
   "@
    lxvp%X1 %x0,%1
+   #
    stxvp%X0 %x1,%0
+   #
    #"
   "&& reload_completed
-   && (!MEM_P (operands[0]) && !MEM_P (operands[1]))"
+   && ((MEM_P (operands[0]) && !TARGET_STXVP)
+       || (MEM_P (operands[1]) && !TARGET_LXVP)
+       || (!MEM_P (operands[0]) && !MEM_P (operands[1])))"
   [(const_int 0)]
 {
   rs6000_split_multireg_move (operands[0], operands[1]);
   DONE;
 }
-  [(set_attr "type" "vecload,vecstore,veclogical")
+  [(set_attr "type" "vecload,vecload,vecstore,vecstore,veclogical")
    (set_attr "size" "256")
-   (set_attr "length" "*,*,8")])
+   (set_attr "length" "*,8,*,8,8")
+   (set_attr "isa" "lxvp,*,stxvp,*,*")])
 
 \f
 ;; Vector quad support.  XOmode can only live in FPRs.
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index efe9adce1f8..4bfc62d930b 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -2576,6 +2576,12 @@ rs6000_debug_reg_global (void)
   if (TARGET_DIRECT_MOVE_128)
     fprintf (stderr, DEBUG_FMT_D, "VSX easy 64-bit mfvsrld element",
 	     (int)VECTOR_ELEMENT_MFVSRLD_64BIT);
+
+  if (TARGET_MMA)
+    fprintf (stderr, DEBUG_FMT_ID "%s, %s\n",
+	     "vector_pair",
+	     TARGET_LXVP ? "lxvp" : "no-lxvp",
+	     TARGET_STXVP ? "stxvp" : "no-stxvp");
 }
 
 \f
@@ -2711,7 +2717,9 @@ rs6000_setup_reg_addr_masks (void)
 	  /* Vector pairs can do both indexed and offset loads if the
 	     instructions are enabled, otherwise they can only do offset loads
 	     since it will be broken into two vector moves.  Vector quads can
-	     only do offset loads.  */
+	     only do offset loads.  If the user restricted generation of either
+	     of the LXVP or STXVP instructions, do not allow indexed mode so
+	     that we can split the load/store.  */
 	  else if ((addr_mask != 0) && TARGET_MMA
 		   && (m2 == OOmode || m2 == XOmode))
 	    {
@@ -2719,7 +2727,7 @@ rs6000_setup_reg_addr_masks (void)
 	      if (rc == RELOAD_REG_FPR || rc == RELOAD_REG_VMX)
 		{
 		  addr_mask |= RELOAD_REG_QUAD_OFFSET;
-		  if (m2 == OOmode)
+		  if (m2 == OOmode && TARGET_LXVP && TARGET_STXVP)
 		    addr_mask |= RELOAD_REG_INDEXED;
 		}
 	    }
@@ -4405,6 +4413,18 @@ rs6000_option_override_internal (bool global_init_p)
       rs6000_isa_flags &= ~OPTION_MASK_MMA;
     }
 
+  /* Warn if -mlxvp or -mstxvp are used and MMA is not set.  */
+  if (!TARGET_MMA)
+    {
+      if (TARGET_LXVP && OPTION_SET_P(TARGET_LXVP))
+	warning (0, "%qs should not be used unless you use %qs",
+		 "-mlxvp", "-mmma");
+
+      if (TARGET_STXVP && OPTION_SET_P(TARGET_STXVP))
+	warning (0, "%qs should not be used unless you use %qs",
+		 "-mstxvp", "-mmma");
+    }
+
   /* Enable power10 fusion if we are tuning for power10, even if we aren't
      generating power10 instructions.  */
   if (!(rs6000_isa_flags_explicit & OPTION_MASK_P10_FUSION))
@@ -24324,6 +24344,12 @@ static struct rs6000_opt_var const rs6000_opt_vars[] =
   { "speculate-indirect-jumps",
     offsetof (struct gcc_options, x_rs6000_speculate_indirect_jumps),
     offsetof (struct cl_target_option, x_rs6000_speculate_indirect_jumps), },
+  { "lxvp",
+    offsetof (struct gcc_options, x_TARGET_LXVP),
+    offsetof (struct cl_target_option, x_TARGET_LXVP), },
+  { "stxvp",
+    offsetof (struct gcc_options, x_TARGET_STXVP),
+    offsetof (struct cl_target_option, x_TARGET_STXVP), },
 };
 
 /* Inner function to handle attribute((target("..."))) and #pragma GCC target
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 9cb14bfcb7f..02de5afcd18 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -355,7 +355,7 @@
   (const (symbol_ref "(enum attr_cpu) rs6000_tune")))
 
 ;; The ISA we implement.
-(define_attr "isa" "any,p5,p6,p7,p7v,p8v,p9,p9v,p9kf,p9tf,p10"
+(define_attr "isa" "any,p5,p6,p7,p7v,p8v,p9,p9v,p9kf,p9tf,p10,lxvp,stxvp"
   (const_string "any"))
 
 ;; Is this alternative enabled for the current CPU/ISA/etc.?
@@ -403,6 +403,14 @@
      (and (eq_attr "isa" "p10")
 	  (match_test "TARGET_POWER10"))
      (const_int 1)
+
+     (and (eq_attr "isa" "lxvp")
+	  (match_test "TARGET_LXVP"))
+     (const_int 1)
+
+     (and (eq_attr "isa" "stxvp")
+	  (match_test "TARGET_STXVP"))
+     (const_int 1)
     ] (const_int 0)))
 
 ;; If this instruction is microcoded on the CELL processor
diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt
index bde6d3ff664..663f0578f30 100644
--- a/gcc/config/rs6000/rs6000.opt
+++ b/gcc/config/rs6000/rs6000.opt
@@ -597,6 +597,14 @@ mmma
 Target Mask(MMA) Var(rs6000_isa_flags)
 Generate (do not generate) MMA instructions.
 
+mlxvp
+Target Undocumented Var(TARGET_LXVP) Init(1) Save
+Generate (do not generate) the LXVP instruction if -mmma is enabled.
+
+mstxvp
+Target Undocumented Var(TARGET_STXVP) Init(1) Save
+Generate (do not generate) the STXVP instruction if -mmma is enabled.
+
 mrelative-jumptables
 Target Undocumented Var(rs6000_relative_jumptables) Init(1) Save
 
diff --git a/gcc/testsuite/gcc.target/powerpc/p10-lxvp-stxvp.c b/gcc/testsuite/gcc.target/powerpc/p10-lxvp-stxvp.c
new file mode 100644
index 00000000000..25f6df4611f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/p10-lxvp-stxvp.c
@@ -0,0 +1,56 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target power10_ok } */
+/* { dg-options "-mdejagnu-cpu=power10 -O2" } */
+
+#include <stddef.h>
+
+/* Test whether we can control lxvp and stxvp.  */
+
+#pragma GCC target ("no-lxvp,no-stxvp")
+
+void
+no_vector_pair (__vector_pair *dest,
+		__vector_pair *src,
+		size_t n,
+		size_t m)
+{
+  dest[n] = src[m];		/* 2 lxv + 2 stxv.  */
+}
+
+#pragma GCC target ("lxvp,no-stxvp")
+
+void
+vector_pair_load (__vector_pair *dest,
+		  __vector_pair *src,
+		  size_t n,
+		  size_t m)
+{
+  dest[n] = src[m];		/* 1 lxvpx + 2 stxv.  */
+}
+
+#pragma GCC target ("no-lxvp,stxvp")
+
+void
+vector_pair_store (__vector_pair *dest,
+		   __vector_pair *src,
+		   size_t n,
+		   size_t m)
+{
+  dest[n] = src[m];		/* 2 lxv + 1 stxvpx.  */
+}
+
+#pragma GCC target ("lxvp,stxvp")
+
+void
+vector_pair_both (__vector_pair *dest,
+		  __vector_pair *src,
+		  size_t n,
+		  size_t m)
+{
+  dest[n] = src[m];		/* 1 lxvpx + 1 stxvpx.  */
+}
+
+/* { dg-final { scan-assembler-times {\mlxv\M}    4 } } */
+/* { dg-final { scan-assembler-times {\mlxvpx\M}  2 } } */
+/* { dg-final { scan-assembler-times {\mstxv\M}   4 } } */
+/* { dg-final { scan-assembler-times {\mstxvpx\M} 2 } } */