From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1005) id 2636D3858D35; Fri, 15 Sep 2023 19:14:45 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 2636D3858D35 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1694805285; bh=N+buw23RySQnqyxSLwFrxh3TsPzuWIe0rIqsqpgtIa0=; h=From:To:Subject:Date:From; b=am/R/zL9KUxnVqfmfl8m5Zi3ItWG/8aQ+tfVDoqVtAZ03eGdclQt0y44XJvd6TUDz t2E7xb16TrOURVduelWR6qgJlRqtIl/AJRO0okUEANrYroXB7VIbRj9XhVOY8l278B CleXZcQPZfW1lZY0fRCmrgvcFVUesbk9DeuJgZ9k= Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Michael Meissner To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/users/meissner/heads/work134-vsubreg)] Peter's patch for subreg support. X-Act-Checkin: gcc X-Git-Author: Michael Meissner X-Git-Refname: refs/users/meissner/heads/work134-vsubreg X-Git-Oldrev: 463837a038c0674c1079e14a15ed9b45377b3b1d X-Git-Newrev: bd41048c89a39cae30cdf3214a20d723293e980b Message-Id: <20230915191445.2636D3858D35@sourceware.org> Date: Fri, 15 Sep 2023 19:14:45 +0000 (GMT) List-Id: https://gcc.gnu.org/g:bd41048c89a39cae30cdf3214a20d723293e980b commit bd41048c89a39cae30cdf3214a20d723293e980b Author: Michael Meissner Date: Fri Sep 15 15:14:22 2023 -0400 Peter's patch for subreg support. 2023-09-15 Peter Bergner gcc/ PR target/109116 * gcc/config/rs6000/mma.md (vsx_disassemble_pair): Use SUBREG's instead of UNSPEC's. (mma_disassemble_acc): Likewise. Diff: --- gcc/config/rs6000/mma.md | 50 ++++-------------------------------------------- 1 file changed, 4 insertions(+), 46 deletions(-) diff --git a/gcc/config/rs6000/mma.md b/gcc/config/rs6000/mma.md index 70ba5b70c1b..5ad96e962a7 100644 --- a/gcc/config/rs6000/mma.md +++ b/gcc/config/rs6000/mma.md @@ -403,29 +403,8 @@ (match_operand 2 "const_0_to_1_operand")] "TARGET_MMA" { - rtx src; - int regoff = INTVAL (operands[2]); - src = gen_rtx_UNSPEC (V16QImode, - gen_rtvec (2, operands[1], GEN_INT (regoff)), - UNSPEC_MMA_EXTRACT); - emit_move_insn (operands[0], src); - DONE; -}) - -(define_insn_and_split "*vsx_disassemble_pair" - [(set (match_operand:V16QI 0 "mma_disassemble_output_operand" "=mwa") - (unspec:V16QI [(match_operand:OO 1 "vsx_register_operand" "wa") - (match_operand 2 "const_0_to_1_operand")] - UNSPEC_MMA_EXTRACT))] - "TARGET_MMA - && vsx_register_operand (operands[1], OOmode)" - "#" - "&& reload_completed" - [(const_int 0)] -{ - int reg = REGNO (operands[1]); - int regoff = INTVAL (operands[2]); - rtx src = gen_rtx_REG (V16QImode, reg + regoff); + int regoff = INTVAL (operands[2]) * GET_MODE_SIZE (V16QImode); + rtx src = simplify_gen_subreg (V16QImode, operands[1], OOmode, regoff); emit_move_insn (operands[0], src); DONE; }) @@ -477,29 +456,8 @@ (match_operand 2 "const_0_to_3_operand")] "TARGET_MMA" { - rtx src; - int regoff = INTVAL (operands[2]); - src = gen_rtx_UNSPEC (V16QImode, - gen_rtvec (2, operands[1], GEN_INT (regoff)), - UNSPEC_MMA_EXTRACT); - emit_move_insn (operands[0], src); - DONE; -}) - -(define_insn_and_split "*mma_disassemble_acc" - [(set (match_operand:V16QI 0 "mma_disassemble_output_operand" "=mwa") - (unspec:V16QI [(match_operand:XO 1 "fpr_reg_operand" "d") - (match_operand 2 "const_0_to_3_operand")] - UNSPEC_MMA_EXTRACT))] - "TARGET_MMA - && fpr_reg_operand (operands[1], XOmode)" - "#" - "&& reload_completed" - [(const_int 0)] -{ - int reg = REGNO (operands[1]); - int regoff = INTVAL (operands[2]); - rtx src = gen_rtx_REG (V16QImode, reg + regoff); + int regoff = INTVAL (operands[2]) * GET_MODE_SIZE (V16QImode); + rtx src = simplify_gen_subreg (V16QImode, operands[1], XOmode, regoff); emit_move_insn (operands[0], src); DONE; })