From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 7928) id A6E2C3858C60; Mon, 18 Sep 2023 11:45:30 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org A6E2C3858C60 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1695037530; bh=4cdZRCzSHYEQCum98m3HQPylmWB0rW+3D3mz7SUlBvY=; h=From:To:Subject:Date:From; b=RzuAwn9tVeqRRxqsqGiqUQO2jmBsyQI2utyVAvnqK4MJ94XHBL3ZgaisQd4ko+zFf nHWVL1Rg9IdzcuhywCpSo5mRbYhB3N/byw3b4410bXABm2jkFPxBzwnKAJHkjxyljY 3XF21lOInSJAXQNHlMJqe5ByebbuAe9IHo1Yqaa4= MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="utf-8" From: Lehua Ding To: gcc-cvs@gcc.gnu.org Subject: [gcc r14-4093] RISC-V: Support VLS reduction X-Act-Checkin: gcc X-Git-Author: Juzhe-Zhong X-Git-Refname: refs/heads/trunk X-Git-Oldrev: 12755fe40b2474554a01815b18c6b9956a513137 X-Git-Newrev: 71e0f38dcb73e4cdfe61fc28821551b325320302 Message-Id: <20230918114530.A6E2C3858C60@sourceware.org> Date: Mon, 18 Sep 2023 11:45:30 +0000 (GMT) List-Id: https://gcc.gnu.org/g:71e0f38dcb73e4cdfe61fc28821551b325320302 commit r14-4093-g71e0f38dcb73e4cdfe61fc28821551b325320302 Author: Juzhe-Zhong Date: Sat Sep 16 23:01:30 2023 +0800 RISC-V: Support VLS reduction Notice previous VLS reduction patch is missing some codes which cause multiple ICE: FAIL: gcc.target/riscv/rvv/autovec/reduc/reduc_run-2.c (internal compiler error: in code_for_pred, at ./insn-opinit.h:1560) FAIL: gcc.target/riscv/rvv/autovec/reduc/reduc_run-2.c (internal compiler error: in code_for_pred, at ./insn-opinit.h:1560) FAIL: gcc.target/riscv/rvv/autovec/reduc/reduc_run-2.c (internal compiler error: in code_for_pred, at ./insn-opinit.h:1560) FAIL: gcc.target/riscv/rvv/autovec/reduc/reduc_run-2.c (internal compiler error: in code_for_pred, at ./insn-opinit.h:1560) FAIL: gcc.target/riscv/rvv/autovec/reduc/reduc_run-2.c (internal compiler error: in code_for_pred, at ./insn-opinit.h:1560) FAIL: gcc.target/riscv/rvv/autovec/reduc/reduc_run-2.c (internal compiler error: in code_for_pred, at ./insn-opinit.h:1560) FAIL: gcc.target/riscv/rvv/autovec/reduc/reduc_run-2.c (internal compiler error: in code_for_pred, at ./insn-opinit.h:1560) FAIL: gcc.target/riscv/rvv/autovec/reduc/reduc_run-2.c (internal compiler error: in code_for_pred, at ./insn-opinit.h:1560) FAIL: gcc.target/riscv/rvv/autovec/reduc/reduc_run-2.c (test for excess errors) FAIL: gcc.target/riscv/rvv/autovec/reduc/reduc_run-2.c (test for excess errors) FAIL: gcc.target/riscv/rvv/autovec/reduc/reduc_run-2.c (test for excess errors) FAIL: gcc.target/riscv/rvv/autovec/reduc/reduc_run-2.c (test for excess errors) FAIL: gcc.target/riscv/rvv/autovec/reduc/reduc_run-2.c (test for excess errors) FAIL: gcc.target/riscv/rvv/autovec/reduc/reduc_run-2.c (test for excess errors) FAIL: gcc.target/riscv/rvv/autovec/reduc/reduc_run-2.c (test for excess errors) FAIL: gcc.target/riscv/rvv/autovec/reduc/reduc_run-2.c (test for excess errors) FAIL: gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-run.c -std=c99 -O3 -ftree-vectorize --param riscv-autovec-preference=fixed-vlmax (test for excess errors) FAIL: gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-runu.c -std=c99 -O3 -ftree-vectorize --param riscv-autovec-preference=fixed-vlmax (test for excess errors) FAIL: gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-run.c -std=c99 -O3 -ftree-vectorize --param riscv-autovec-preference=fixed-vlmax (test for excess errors) FAIL: gcc.target/riscv/rvv/autovec/vls/reduc-1.c -O3 -ftree-vectorize --param riscv-autovec-preference=scalable scan-assembler-times vredsum\\.vs 22 FAIL: gcc.target/riscv/rvv/autovec/vls/reduc-10.c -O3 -ftree-vectorize --param riscv-autovec-preference=scalable scan-assembler-times vredmax\\.vs 9 FAIL: gcc.target/riscv/rvv/autovec/vls/reduc-10.c -O3 -ftree-vectorize --param riscv-autovec-preference=scalable scan-assembler-times vredmaxu\\.vs 9 FAIL: gcc.target/riscv/rvv/autovec/vls/reduc-10.c -O3 -ftree-vectorize --param riscv-autovec-preference=scalable scan-assembler-times vredmin\\.vs 9 FAIL: gcc.target/riscv/rvv/autovec/vls/reduc-10.c -O3 -ftree-vectorize --param riscv-autovec-preference=scalable scan-assembler-times vredminu\\.vs 9 FAIL: gcc.target/riscv/rvv/autovec/vls/reduc-11.c -O3 -ftree-vectorize --param riscv-autovec-preference=scalable scan-assembler-times vredmax\\.vs 8 FAIL: gcc.target/riscv/rvv/autovec/vls/reduc-11.c -O3 -ftree-vectorize --param riscv-autovec-preference=scalable scan-assembler-times vredmaxu\\.vs 8 FAIL: gcc.target/riscv/rvv/autovec/vls/reduc-11.c -O3 -ftree-vectorize --param riscv-autovec-preference=scalable scan-assembler-times vredmin\\.vs 8 FAIL: gcc.target/riscv/rvv/autovec/vls/reduc-11.c -O3 -ftree-vectorize --param riscv-autovec-preference=scalable scan-assembler-times vredminu\\.vs 8 FAIL: gcc.target/riscv/rvv/autovec/vls/reduc-12.c -O3 -ftree-vectorize --param riscv-autovec-preference=scalable scan-assembler-times vfredmax\\.vs 10 FAIL: gcc.target/riscv/rvv/autovec/vls/reduc-12.c -O3 -ftree-vectorize --param riscv-autovec-preference=scalable scan-assembler-times vfredmin\\.vs 10 FAIL: gcc.target/riscv/rvv/autovec/vls/reduc-13.c -O3 -ftree-vectorize --param riscv-autovec-preference=scalable scan-assembler-times vfredmax\\.vs 9 FAIL: gcc.target/riscv/rvv/autovec/vls/reduc-13.c -O3 -ftree-vectorize --param riscv-autovec-preference=scalable scan-assembler-times vfredmin\\.vs 9 FAIL: gcc.target/riscv/rvv/autovec/vls/reduc-14.c -O3 -ftree-vectorize --param riscv-autovec-preference=scalable scan-assembler-times vfredmax\\.vs 8 FAIL: gcc.target/riscv/rvv/autovec/vls/reduc-14.c -O3 -ftree-vectorize --param riscv-autovec-preference=scalable scan-assembler-times vfredmin\\.vs 8 FAIL: gcc.target/riscv/rvv/autovec/vls/reduc-15.c -O3 -ftree-vectorize --param riscv-autovec-preference=scalable scan-assembler-times vredand\\.vs 22 FAIL: gcc.target/riscv/rvv/autovec/vls/reduc-15.c -O3 -ftree-vectorize --param riscv-autovec-preference=scalable scan-assembler-times vredor\\.vs 22 FAIL: gcc.target/riscv/rvv/autovec/vls/reduc-15.c -O3 -ftree-vectorize --param riscv-autovec-preference=scalable scan-assembler-times vredxor\\.vs 22 FAIL: gcc.target/riscv/rvv/autovec/vls/reduc-16.c -O3 -ftree-vectorize --param riscv-autovec-preference=scalable scan-assembler-times vredand\\.vs 20 FAIL: gcc.target/riscv/rvv/autovec/vls/reduc-16.c -O3 -ftree-vectorize --param riscv-autovec-preference=scalable scan-assembler-times vredor\\.vs 20 FAIL: gcc.target/riscv/rvv/autovec/vls/reduc-16.c -O3 -ftree-vectorize --param riscv-autovec-preference=scalable scan-assembler-times vredxor\\.vs 20 FAIL: gcc.target/riscv/rvv/autovec/vls/reduc-17.c -O3 -ftree-vectorize --param riscv-autovec-preference=scalable scan-assembler-times vredand\\.vs 18 FAIL: gcc.target/riscv/rvv/autovec/vls/reduc-17.c -O3 -ftree-vectorize --param riscv-autovec-preference=scalable scan-assembler-times vredor\\.vs 18 FAIL: gcc.target/riscv/rvv/autovec/vls/reduc-17.c -O3 -ftree-vectorize --param riscv-autovec-preference=scalable scan-assembler-times vredxor\\.vs 18 FAIL: gcc.target/riscv/rvv/autovec/vls/reduc-18.c -O3 -ftree-vectorize --param riscv-autovec-preference=scalable scan-assembler-times vredand\\.vs 16 FAIL: gcc.target/riscv/rvv/autovec/vls/reduc-18.c -O3 -ftree-vectorize --param riscv-autovec-preference=scalable scan-assembler-times vredor\\.vs 16 FAIL: gcc.target/riscv/rvv/autovec/vls/reduc-18.c -O3 -ftree-vectorize --param riscv-autovec-preference=scalable scan-assembler-times vredxor\\.vs 16 FAIL: gcc.target/riscv/rvv/autovec/vls/reduc-19.c -O3 -ftree-vectorize --param riscv-autovec-preference=scalable (internal compiler error: in code_for_pred, at ./insn-opinit.h:1560) FAIL: gcc.target/riscv/rvv/autovec/vls/reduc-19.c -O3 -ftree-vectorize --param riscv-autovec-preference=scalable (test for excess errors) FAIL: gcc.target/riscv/rvv/autovec/vls/reduc-2.c -O3 -ftree-vectorize --param riscv-autovec-preference=scalable scan-assembler-times vredsum\\.vs 20 FAIL: gcc.target/riscv/rvv/autovec/vls/reduc-20.c -O3 -ftree-vectorize --param riscv-autovec-preference=scalable (internal compiler error: in code_for_pred, at ./insn-opinit.h:1560) FAIL: gcc.target/riscv/rvv/autovec/vls/reduc-20.c -O3 -ftree-vectorize --param riscv-autovec-preference=scalable (test for excess errors) FAIL: gcc.target/riscv/rvv/autovec/vls/reduc-21.c -O3 -ftree-vectorize --param riscv-autovec-preference=scalable (internal compiler error: in code_for_pred, at ./insn-opinit.h:1560) FAIL: gcc.target/riscv/rvv/autovec/vls/reduc-21.c -O3 -ftree-vectorize --param riscv-autovec-preference=scalable (test for excess errors) FAIL: gcc.target/riscv/rvv/autovec/vls/reduc-3.c -O3 -ftree-vectorize --param riscv-autovec-preference=scalable scan-assembler-times vredsum\\.vs 18 FAIL: gcc.target/riscv/rvv/autovec/vls/reduc-4.c -O3 -ftree-vectorize --param riscv-autovec-preference=scalable scan-assembler-times vredsum\\.vs 16 FAIL: gcc.target/riscv/rvv/autovec/vls/reduc-5.c -O3 -ftree-vectorize --param riscv-autovec-preference=scalable scan-assembler-times vfredusum\\.vs 10 FAIL: gcc.target/riscv/rvv/autovec/vls/reduc-6.c -O3 -ftree-vectorize --param riscv-autovec-preference=scalable scan-assembler-times vfredusum\\.vs 9 FAIL: gcc.target/riscv/rvv/autovec/vls/reduc-7.c -O3 -ftree-vectorize --param riscv-autovec-preference=scalable scan-assembler-times vfredusum\\.vs 8 FAIL: gcc.target/riscv/rvv/autovec/vls/reduc-8.c -O3 -ftree-vectorize --param riscv-autovec-preference=scalable scan-assembler-times vredmax\\.vs 11 FAIL: gcc.target/riscv/rvv/autovec/vls/reduc-8.c -O3 -ftree-vectorize --param riscv-autovec-preference=scalable scan-assembler-times vredmaxu\\.vs 11 FAIL: gcc.target/riscv/rvv/autovec/vls/reduc-8.c -O3 -ftree-vectorize --param riscv-autovec-preference=scalable scan-assembler-times vredmin\\.vs 11 FAIL: gcc.target/riscv/rvv/autovec/vls/reduc-8.c -O3 -ftree-vectorize --param riscv-autovec-preference=scalable scan-assembler-times vredminu\\.vs 11 FAIL: gcc.target/riscv/rvv/autovec/vls/reduc-9.c -O3 -ftree-vectorize --param riscv-autovec-preference=scalable scan-assembler-times vredmax\\.vs 10 FAIL: gcc.target/riscv/rvv/autovec/vls/reduc-9.c -O3 -ftree-vectorize --param riscv-autovec-preference=scalable scan-assembler-times vredmaxu\\.vs 10 FAIL: gcc.target/riscv/rvv/autovec/vls/reduc-9.c -O3 -ftree-vectorize --param riscv-autovec-preference=scalable scan-assembler-times vredmin\\.vs 10 FAIL: gcc.target/riscv/rvv/autovec/vls/reduc-9.c -O3 -ftree-vectorize --param riscv-autovec-preference=scalable scan-assembler-times vredminu\\.vs 10 Committed. gcc/ChangeLog: * config/riscv/autovec.md: Add VLS modes. * config/riscv/vector-iterators.md: Ditto. * config/riscv/vector.md: Ditto. Diff: --- gcc/config/riscv/autovec.md | 22 +++++----- gcc/config/riscv/vector-iterators.md | 80 ++++++++++++++++++++++++++++++++++++ gcc/config/riscv/vector.md | 6 +-- 3 files changed, 94 insertions(+), 14 deletions(-) diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md index 1c22f96ec26..493d5745485 100644 --- a/gcc/config/riscv/autovec.md +++ b/gcc/config/riscv/autovec.md @@ -2089,7 +2089,7 @@ (define_insn_and_split "reduc_plus_scal_" [(set (match_operand: 0 "register_operand") (unspec: [ - (match_operand:VI 1 "register_operand") + (match_operand:V_VLSI 1 "register_operand") ] UNSPEC_REDUC_SUM))] "TARGET_VECTOR && can_create_pseudo_p ()" "#" @@ -2104,7 +2104,7 @@ (define_expand "reduc_smax_scal_" [(match_operand: 0 "register_operand") - (match_operand:VI 1 "register_operand")] + (match_operand:V_VLSI 1 "register_operand")] "TARGET_VECTOR" { int prec = GET_MODE_PRECISION (mode); @@ -2116,7 +2116,7 @@ (define_expand "reduc_umax_scal_" [(match_operand: 0 "register_operand") - (match_operand:VI 1 "register_operand")] + (match_operand:V_VLSI 1 "register_operand")] "TARGET_VECTOR" { riscv_vector::expand_reduction (UNSPEC_REDUC_MAXU, riscv_vector::REDUCE_OP, @@ -2126,7 +2126,7 @@ (define_expand "reduc_smin_scal_" [(match_operand: 0 "register_operand") - (match_operand:VI 1 "register_operand")] + (match_operand:V_VLSI 1 "register_operand")] "TARGET_VECTOR" { int prec = GET_MODE_PRECISION (mode); @@ -2138,7 +2138,7 @@ (define_expand "reduc_umin_scal_" [(match_operand: 0 "register_operand") - (match_operand:VI 1 "register_operand")] + (match_operand:V_VLSI 1 "register_operand")] "TARGET_VECTOR" { int prec = GET_MODE_PRECISION (mode); @@ -2150,7 +2150,7 @@ (define_expand "reduc_and_scal_" [(match_operand: 0 "register_operand") - (match_operand:VI 1 "register_operand")] + (match_operand:V_VLSI 1 "register_operand")] "TARGET_VECTOR" { riscv_vector::expand_reduction (UNSPEC_REDUC_AND, riscv_vector::REDUCE_OP, @@ -2160,7 +2160,7 @@ (define_expand "reduc_ior_scal_" [(match_operand: 0 "register_operand") - (match_operand:VI 1 "register_operand")] + (match_operand:V_VLSI 1 "register_operand")] "TARGET_VECTOR" { riscv_vector::expand_reduction (UNSPEC_REDUC_OR, riscv_vector::REDUCE_OP, @@ -2170,7 +2170,7 @@ (define_expand "reduc_xor_scal_" [(match_operand: 0 "register_operand") - (match_operand:VI 1 "register_operand")] + (match_operand:V_VLSI 1 "register_operand")] "TARGET_VECTOR" { riscv_vector::expand_reduction (UNSPEC_REDUC_XOR, riscv_vector::REDUCE_OP, @@ -2190,7 +2190,7 @@ (define_insn_and_split "reduc_plus_scal_" [(set (match_operand: 0 "register_operand") (unspec: [ - (match_operand:VF 1 "register_operand") + (match_operand:V_VLSF 1 "register_operand") ] UNSPEC_REDUC_SUM_UNORDERED))] "TARGET_VECTOR && can_create_pseudo_p ()" "#" @@ -2206,7 +2206,7 @@ (define_expand "reduc_smax_scal_" [(match_operand: 0 "register_operand") - (match_operand:VF 1 "register_operand")] + (match_operand:V_VLSF 1 "register_operand")] "TARGET_VECTOR" { REAL_VALUE_TYPE rv; @@ -2219,7 +2219,7 @@ (define_expand "reduc_smin_scal_" [(match_operand: 0 "register_operand") - (match_operand:VF 1 "register_operand")] + (match_operand:V_VLSF 1 "register_operand")] "TARGET_VECTOR" { REAL_VALUE_TYPE rv; diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md index fa9892cebc1..0b395e65228 100644 --- a/gcc/config/riscv/vector-iterators.md +++ b/gcc/config/riscv/vector-iterators.md @@ -1300,6 +1300,86 @@ (RVVM8SF "RVVM1SF") (RVVM4SF "RVVM1SF") (RVVM2SF "RVVM1SF") (RVVM1SF "RVVM1SF") (RVVMF2SF "RVVM1SF") (RVVM8DF "RVVM1DF") (RVVM4DF "RVVM1DF") (RVVM2DF "RVVM1DF") (RVVM1DF "RVVM1DF") + + (V1QI "RVVM1QI") + (V2QI "RVVM1QI") + (V4QI "RVVM1QI") + (V8QI "RVVM1QI") + (V16QI "RVVM1QI") + (V32QI "RVVM1QI") + (V64QI "RVVM1QI") + (V128QI "RVVM1QI") + (V256QI "RVVM1QI") + (V512QI "RVVM1QI") + (V1024QI "RVVM1QI") + (V2048QI "RVVM1QI") + (V4096QI "RVVM1QI") + (V1HI "RVVM1HI") + (V2HI "RVVM1HI") + (V4HI "RVVM1HI") + (V8HI "RVVM1HI") + (V16HI "RVVM1HI") + (V32HI "RVVM1HI") + (V64HI "RVVM1HI") + (V128HI "RVVM1HI") + (V256HI "RVVM1HI") + (V512HI "RVVM1HI") + (V1024HI "RVVM1HI") + (V2048HI "RVVM1HI") + (V1SI "RVVM1SI") + (V2SI "RVVM1SI") + (V4SI "RVVM1SI") + (V8SI "RVVM1SI") + (V16SI "RVVM1SI") + (V32SI "RVVM1SI") + (V64SI "RVVM1SI") + (V128SI "RVVM1SI") + (V256SI "RVVM1SI") + (V512SI "RVVM1SI") + (V1024SI "RVVM1SI") + (V1DI "RVVM1DI") + (V2DI "RVVM1DI") + (V4DI "RVVM1DI") + (V8DI "RVVM1DI") + (V16DI "RVVM1DI") + (V32DI "RVVM1DI") + (V64DI "RVVM1DI") + (V128DI "RVVM1DI") + (V256DI "RVVM1DI") + (V512DI "RVVM1DI") + (V1HF "RVVM1HF") + (V2HF "RVVM1HF") + (V4HF "RVVM1HF") + (V8HF "RVVM1HF") + (V16HF "RVVM1HF") + (V32HF "RVVM1HF") + (V64HF "RVVM1HF") + (V128HF "RVVM1HF") + (V256HF "RVVM1HF") + (V512HF "RVVM1HF") + (V1024HF "RVVM1HF") + (V2048HF "RVVM1HF") + (V1SF "RVVM1SF") + (V2SF "RVVM1SF") + (V4SF "RVVM1SF") + (V8SF "RVVM1SF") + (V16SF "RVVM1SF") + (V32SF "RVVM1SF") + (V64SF "RVVM1SF") + (V128SF "RVVM1SF") + (V256SF "RVVM1SF") + (V512SF "RVVM1SF") + (V1024SF "RVVM1SF") + (V1DF "RVVM1DF") + (V2DF "RVVM1DF") + (V4DF "RVVM1DF") + (V8DF "RVVM1DF") + (V16DF "RVVM1DF") + (V32DF "RVVM1DF") + (V64DF "RVVM1DF") + (V128DF "RVVM1DF") + (V256DF "RVVM1DF") + (V512DF "RVVM1DF") ]) (define_mode_attr V_EXT_LMUL1 [ diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index 44a344796ea..39b550c1bff 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -7906,7 +7906,7 @@ (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (unspec: [ - (match_operand:VI 3 "register_operand" " vr, vr") + (match_operand:V_VLSI 3 "register_operand" " vr, vr") (match_operand: 4 "register_operand" " vr, vr") ] ANY_REDUC) (match_operand: 2 "vector_merge_operand" " vu, 0")] UNSPEC_REDUC))] @@ -7948,7 +7948,7 @@ (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (unspec: [ - (match_operand:VF 3 "register_operand" " vr, vr") + (match_operand:V_VLSF 3 "register_operand" " vr, vr") (match_operand: 4 "register_operand" " vr, vr") ] ANY_FREDUC) (match_operand: 2 "vector_merge_operand" " vu, 0")] UNSPEC_REDUC))] @@ -7971,7 +7971,7 @@ (reg:SI VTYPE_REGNUM) (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE) (unspec: [ - (match_operand:VF 3 "register_operand" " vr, vr") + (match_operand:V_VLSF 3 "register_operand" " vr, vr") (match_operand: 4 "register_operand" " vr, vr") ] ANY_FREDUC_SUM) (match_operand: 2 "vector_merge_operand" " vu, 0")] UNSPEC_REDUC))]