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From: Jeff Law <law@gcc.gnu.org>
To: gcc-cvs@gcc.gnu.org
Subject: [gcc(refs/vendors/riscv/heads/gcc-13-with-riscv-opts)] RISC-V: Add Types to Un-Typed Thead Instructions
Date: Mon, 18 Sep 2023 18:24:38 +0000 (GMT) [thread overview]
Message-ID: <20230918182438.DBB7A3857C44@sourceware.org> (raw)
https://gcc.gnu.org/g:7ac52d2caddf75bce64d3880ea23c55ecaf93dd8
commit 7ac52d2caddf75bce64d3880ea23c55ecaf93dd8
Author: Edwin Lu <ewlu@rivosinc.com>
Date: Mon Sep 11 10:00:34 2023 -0700
RISC-V: Add Types to Un-Typed Thead Instructions
Updates the THEAD instructions to ensure that no insn is left
without a type attribute.
Tested for regressions using rv32/64 multilib for linux/newlib.
gcc/Changelog:
* config/riscv/thead.md: Update types
Signed-off-by: Edwin Lu <ewlu@rivosinc.com>
(cherry picked from commit 316d57da5bb9205b946afc56d78582fee874e4b5)
Diff:
---
gcc/config/riscv/thead.md | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/gcc/config/riscv/thead.md b/gcc/config/riscv/thead.md
index 2287b752ea1..65dbd32536f 100644
--- a/gcc/config/riscv/thead.md
+++ b/gcc/config/riscv/thead.md
@@ -180,6 +180,7 @@
"!TARGET_64BIT && TARGET_XTHEADFMV"
"fmv.w.x\t%0,%2\n\tth.fmv.hw.x\t%0,%1"
[(set_attr "move_type" "move")
+ (set_attr "type" "fmove")
(set_attr "mode" "DF")])
(define_insn "th_fmv_x_w"
@@ -189,6 +190,7 @@
"!TARGET_64BIT && TARGET_XTHEADFMV"
"fmv.x.w\t%0,%1"
[(set_attr "move_type" "move")
+ (set_attr "type" "fmove")
(set_attr "mode" "DF")])
(define_insn "th_fmv_x_hw"
@@ -198,6 +200,7 @@
"!TARGET_64BIT && TARGET_XTHEADFMV"
"th.fmv.x.hw\t%0,%1"
[(set_attr "move_type" "move")
+ (set_attr "type" "fmove")
(set_attr "mode" "DF")])
;; XTheadMac
@@ -333,6 +336,7 @@
&& th_mempair_operands_p (operands, true, <GPR:MODE>mode)"
{ return th_mempair_output_move (operands, true, <GPR:MODE>mode, UNKNOWN); }
[(set_attr "move_type" "load")
+ (set_attr "type" "load")
(set_attr "mode" "<GPR:MODE>")])
;; MEMPAIR store 64/32 bit
@@ -345,6 +349,7 @@
&& th_mempair_operands_p (operands, false, <GPR:MODE>mode)"
{ return th_mempair_output_move (operands, false, <GPR:MODE>mode, UNKNOWN); }
[(set_attr "move_type" "store")
+ (set_attr "type" "store")
(set_attr "mode" "<GPR:MODE>")])
;; MEMPAIR load DI extended signed SI
@@ -357,6 +362,7 @@
&& th_mempair_operands_p (operands, true, SImode)"
{ return th_mempair_output_move (operands, true, SImode, SIGN_EXTEND); }
[(set_attr "move_type" "load")
+ (set_attr "type" "load")
(set_attr "mode" "DI")
(set_attr "length" "8")])
@@ -370,6 +376,7 @@
&& th_mempair_operands_p (operands, true, SImode)"
{ return th_mempair_output_move (operands, true, SImode, ZERO_EXTEND); }
[(set_attr "move_type" "load")
+ (set_attr "type" "load")
(set_attr "mode" "DI")
(set_attr "length" "8")])
reply other threads:[~2023-09-18 18:24 UTC|newest]
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