From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 2119) id A840238582B7; Mon, 18 Sep 2023 18:25:29 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org A840238582B7 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1695061529; bh=wj8Lbw4QXw6Jm46RLCyN3RuYPCVXQVu2QAqhe8Pp8eI=; h=From:To:Subject:Date:From; b=Rsc6PnQf8WYnI3CUtW5NTQezaAO94diHXsuhkw3psU52AKZI2kqzxlK0twNY+NbCj HvtTUy6YADHdCJW6saP6Sy5mgJZb55a6phQAbzyGJGdOJmncMLt6Q3svSxVa0LXGiy YKalWy7v7QiFcxmSEl6lnUDaiiC9/c5gaaxQfCS4= Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Jeff Law To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/vendors/riscv/heads/gcc-13-with-riscv-opts)] RISC-V: Finish Typing Un-Typed Instructions and Turn on Assert X-Act-Checkin: gcc X-Git-Author: Edwin Lu X-Git-Refname: refs/vendors/riscv/heads/gcc-13-with-riscv-opts X-Git-Oldrev: 49eb15ab0b07d1f7b7bbbd156619a2848e16ca6f X-Git-Newrev: 178e88c27caa0109e6f68bba03774900889d0c36 Message-Id: <20230918182529.A840238582B7@sourceware.org> Date: Mon, 18 Sep 2023 18:25:29 +0000 (GMT) List-Id: https://gcc.gnu.org/g:178e88c27caa0109e6f68bba03774900889d0c36 commit 178e88c27caa0109e6f68bba03774900889d0c36 Author: Edwin Lu Date: Tue Sep 12 09:31:40 2023 -0700 RISC-V: Finish Typing Un-Typed Instructions and Turn on Assert Updates autovec instruction that was added after last patch and turns on the assert statement to ensure all new instructions have a type. * config/riscv/autovec-opt.md: Update type * config/riscv/riscv.cc (riscv_sched_variable_issue): Enable assert Reviewed-by: Jeff Law Signed-off-by: Edwin Lu (cherry picked from commit 360c8cad6a727d5afd43017ca1ce9a84c6db61c5) Diff: --- gcc/config/riscv/autovec-opt.md | 3 ++- gcc/config/riscv/riscv.cc | 2 -- 2 files changed, 2 insertions(+), 3 deletions(-) diff --git a/gcc/config/riscv/autovec-opt.md b/gcc/config/riscv/autovec-opt.md index 58e80044f1e..f1d058ce911 100644 --- a/gcc/config/riscv/autovec-opt.md +++ b/gcc/config/riscv/autovec-opt.md @@ -649,7 +649,8 @@ gen_int_mode (GET_MODE_NUNITS (mode), Pmode)}; riscv_vector::expand_cond_len_unop (icode, ops); DONE; -}) +} +[(set_attr "type" "vector")]) ;; Combine vlmax neg and UNSPEC_VCOPYSIGN (define_insn_and_split "*copysign_neg" diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 0ecda795b38..9d04ddd69e0 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -7721,11 +7721,9 @@ riscv_sched_variable_issue (FILE *, int, rtx_insn *insn, int more) if (get_attr_type (insn) == TYPE_GHOST) return 0; -#if 0 /* If we ever encounter an insn with an unknown type, trip an assert so we can find and fix this problem. */ gcc_assert (get_attr_type (insn) != TYPE_UNKNOWN); -#endif return more - 1; }