From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 2119) id BAF63385770A; Mon, 18 Sep 2023 18:27:51 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org BAF63385770A DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1695061671; bh=MSMjLa+BfazY9pLejEakd2+9BVrnVLgzrvZSkFvBNSk=; h=From:To:Subject:Date:From; b=mI+MN47nxlquk5Xl6I/rUOr7fUSZhgbUXdy6qOUNT6o7z+kAn5vd7M/dIpqfT4Wso aK/PrXkBqWp9Ln/UOD5MwY62m0CSg8u/hDrftXr2yfQcZejl9NbdnWnkaSFpFrFEnO J/5gFtzJU0Von9VFZ+C6ot3BKfvqHpsJBALi2/Bk= Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Jeff Law To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/vendors/riscv/heads/gcc-13-with-riscv-opts)] RISC-V: Expand VLS mode to scalar mode move[PR111391] X-Act-Checkin: gcc X-Git-Author: Juzhe-Zhong X-Git-Refname: refs/vendors/riscv/heads/gcc-13-with-riscv-opts X-Git-Oldrev: 5efb369c8dbed53b36b5a6905bd5faebc4a4fe07 X-Git-Newrev: c50b1b3dabb46b5577f26d1d14694cb904187531 Message-Id: <20230918182751.BAF63385770A@sourceware.org> Date: Mon, 18 Sep 2023 18:27:51 +0000 (GMT) List-Id: https://gcc.gnu.org/g:c50b1b3dabb46b5577f26d1d14694cb904187531 commit c50b1b3dabb46b5577f26d1d14694cb904187531 Author: Juzhe-Zhong Date: Thu Sep 14 18:49:52 2023 +0800 RISC-V: Expand VLS mode to scalar mode move[PR111391] This patch fixes https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111391 PR target/111391 gcc/ChangeLog: * config/riscv/autovec.md (@vec_extract): Remove @. (vec_extract): Ditto. * config/riscv/riscv-vsetvl.cc (emit_vsetvl_insn): Fix bug. (pass_vsetvl::local_eliminate_vsetvl_insn): Fix bug. * config/riscv/riscv.cc (riscv_legitimize_move): Expand VLS mode to scalar mode move. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/partial/slp-9.c: Adapt test. * gcc.target/riscv/rvv/autovec/pr111391-1.c: New test. * gcc.target/riscv/rvv/autovec/pr111391-2.c: New test. (cherry picked from commit 86451305d8b2a25e7c6ea6c2f1ee69c419cba3ef) Diff: --- gcc/config/riscv/autovec.md | 2 +- gcc/config/riscv/riscv-vsetvl.cc | 4 +- gcc/config/riscv/riscv.cc | 64 ++++++++++++++++++++++ .../gcc.target/riscv/rvv/autovec/partial/slp-9.c | 1 - .../gcc.target/riscv/rvv/autovec/pr111391-1.c | 28 ++++++++++ .../gcc.target/riscv/rvv/autovec/pr111391-2.c | 10 ++++ 6 files changed, 106 insertions(+), 3 deletions(-) diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md index c6175a3b1f6..aca86554a94 100644 --- a/gcc/config/riscv/autovec.md +++ b/gcc/config/riscv/autovec.md @@ -1442,7 +1442,7 @@ ;; ------------------------------------------------------------------------- ;; ---- [INT,FP] Extract a vector element. ;; ------------------------------------------------------------------------- -(define_expand "@vec_extract" +(define_expand "vec_extract" [(set (match_operand: 0 "register_operand") (vec_select: (match_operand:V_VLS 1 "register_operand") diff --git a/gcc/config/riscv/riscv-vsetvl.cc b/gcc/config/riscv/riscv-vsetvl.cc index dc02246756d..5f031c18df5 100644 --- a/gcc/config/riscv/riscv-vsetvl.cc +++ b/gcc/config/riscv/riscv-vsetvl.cc @@ -649,6 +649,8 @@ emit_vsetvl_insn (enum vsetvl_type insn_type, enum emit_type emit_type, { fprintf (dump_file, "\nInsert vsetvl insn PATTERN:\n"); print_rtl_single (dump_file, pat); + fprintf (dump_file, "\nfor insn:\n"); + print_rtl_single (dump_file, rinsn); } if (emit_type == EMIT_DIRECT) @@ -3867,7 +3869,7 @@ pass_vsetvl::local_eliminate_vsetvl_insn (const bb_info *bb) const skip_one = true; } - curr_avl = get_avl (rinsn); + curr_avl = curr_dem.get_avl (); /* Some instrucion like pred_extract_first don't reqruie avl, so the avl is null, use vl_placeholder for unify the handling diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 762937b0e37..8c766e2e2be 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -2513,6 +2513,70 @@ riscv_legitimize_move (machine_mode mode, rtx dest, rtx src) } return true; } + /* Expand + (set (reg:DI target) (subreg:DI (reg:V8QI reg) 0)) + Expand this data movement instead of simply forbid it since + we can improve the code generation for this following scenario + by RVV auto-vectorization: + (set (reg:V8QI 149) (vec_duplicate:V8QI (reg:QI)) + (set (reg:DI target) (subreg:DI (reg:V8QI reg) 0)) + Since RVV mode and scalar mode are in different REG_CLASS, + we need to explicitly move data from V_REGS to GR_REGS by scalar move. */ + if (SUBREG_P (src) && riscv_v_ext_mode_p (GET_MODE (SUBREG_REG (src)))) + { + machine_mode vmode = GET_MODE (SUBREG_REG (src)); + unsigned int mode_size = GET_MODE_SIZE (mode).to_constant (); + unsigned int vmode_size = GET_MODE_SIZE (vmode).to_constant (); + unsigned int nunits = vmode_size / mode_size; + scalar_mode smode = as_a (mode); + unsigned int index = SUBREG_BYTE (src).to_constant () / mode_size; + unsigned int num = smode == DImode && !TARGET_VECTOR_ELEN_64 ? 2 : 1; + + if (num == 2) + { + /* If we want to extract 64bit value but ELEN < 64, + we use RVV vector mode with EEW = 32 to extract + the highpart and lowpart. */ + smode = SImode; + nunits = nunits * 2; + } + vmode = riscv_vector::get_vector_mode (smode, nunits).require (); + enum insn_code icode + = convert_optab_handler (vec_extract_optab, vmode, smode); + gcc_assert (icode != CODE_FOR_nothing); + rtx v = gen_lowpart (vmode, SUBREG_REG (src)); + + for (unsigned int i = 0; i < num; i++) + { + class expand_operand ops[3]; + rtx result; + if (num == 1) + result = dest; + else if (i == 0) + result = gen_lowpart (smode, dest); + else + result = gen_reg_rtx (smode); + create_output_operand (&ops[0], result, smode); + ops[0].target = 1; + create_input_operand (&ops[1], v, vmode); + create_integer_operand (&ops[2], index + i); + expand_insn (icode, 3, ops); + if (ops[0].value != result) + emit_move_insn (result, ops[0].value); + + if (i == 1) + { + rtx tmp + = expand_binop (Pmode, ashl_optab, gen_lowpart (Pmode, result), + gen_int_mode (32, Pmode), NULL_RTX, 0, + OPTAB_DIRECT); + rtx tmp2 = expand_binop (Pmode, ior_optab, tmp, dest, NULL_RTX, 0, + OPTAB_DIRECT); + emit_move_insn (dest, tmp2); + } + } + return true; + } /* Expand (set (reg:QI target) (mem:QI (address))) to diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-9.c index 5fba27c7a35..7c42438c9d9 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-9.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-9.c @@ -29,4 +29,3 @@ TEST_ALL (VEC_PERM) /* { dg-final { scan-assembler-times {viota.m} 2 } } */ -/* { dg-final { scan-assembler-not {vmv\.v\.i} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr111391-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr111391-1.c new file mode 100644 index 00000000000..a7f64c937c6 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr111391-1.c @@ -0,0 +1,28 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -Wno-int-conversion -Wno-implicit-function -Wno-incompatible-pointer-types -Wno-implicit-function-declaration -Ofast -ftree-vectorize" } */ + +int d (); +typedef struct +{ + int b; +} c; +int +e (char *f, long g) +{ + f += g; + while (g--) + *--f = d; +} + +int +d (c * f) +{ + while (h ()) + switch (f->b) + case 'Q': + { + long a; + e (&a, sizeof (a)); + i (a); + } +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr111391-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr111391-2.c new file mode 100644 index 00000000000..1f170c962e1 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr111391-2.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zve32x_zvl128b -mabi=lp64d -Wno-int-conversion -Wno-implicit-function -Wno-incompatible-pointer-types -Wno-implicit-function-declaration -Ofast -ftree-vectorize" } */ + +#include "pr111391-1.c" + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*2,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 1 } } +/* { dg-final { scan-assembler-times {vmv\.x\.s} 2 } } */ +/* { dg-final { scan-assembler-times {vslidedown.vi\s+v[0-9]+,\s*v[0-9]+,\s*1} 1 } } */ +/* { dg-final { scan-assembler-times {slli\s+[a-x0-9]+,[a-x0-9]+,32} 1 } } */ +/* { dg-final { scan-assembler-times {or\s+[a-x0-9]+,[a-x0-9]+,[a-x0-9]+} 1 } } */