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From: Jeff Law <law@gcc.gnu.org>
To: gcc-cvs@gcc.gnu.org
Subject: [gcc(refs/vendors/riscv/heads/gcc-13-with-riscv-opts)] RISC-V: Remove redundant codes of VLS patterns[NFC]
Date: Mon, 18 Sep 2023 18:27:56 +0000 (GMT) [thread overview]
Message-ID: <20230918182756.CF8F53857357@sourceware.org> (raw)
https://gcc.gnu.org/g:ba0fb660c1d07f4113b92a74316ffe943117a1c3
commit ba0fb660c1d07f4113b92a74316ffe943117a1c3
Author: Juzhe-Zhong <juzhe.zhong@rivai.ai>
Date: Mon Sep 18 10:51:56 2023 +0800
RISC-V: Remove redundant codes of VLS patterns[NFC]
Consider those VLS patterns are the same VLA patterns.
Now extend VI -> V_VLSI and VF -> V_VLSF.
Then remove the redundant codes of VLS patterns.
gcc/ChangeLog:
* config/riscv/autovec-vls.md (<optab><mode>3): Deleted.
(copysign<mode>3): Ditto.
(xorsign<mode>3): Ditto.
(<optab><mode>2): Ditto.
* config/riscv/autovec.md: Extend VLS modes.
(cherry picked from commit 5761dce5d71e3dd013ce4db4c5e9b5e49c6cba23)
Diff:
---
gcc/config/riscv/autovec-vls.md | 138 ----------------------------------------
gcc/config/riscv/autovec.md | 44 ++++++-------
2 files changed, 22 insertions(+), 160 deletions(-)
diff --git a/gcc/config/riscv/autovec-vls.md b/gcc/config/riscv/autovec-vls.md
index d4ed2081537..3488f452e5d 100644
--- a/gcc/config/riscv/autovec-vls.md
+++ b/gcc/config/riscv/autovec-vls.md
@@ -194,141 +194,3 @@
}
[(set_attr "type" "vector")]
)
-
-;; -------------------------------------------------------------------------
-;; ---- [INT] Binary operations
-;; -------------------------------------------------------------------------
-;; Includes:
-;; - vadd.vv/vsub.vv/...
-;; - vadd.vi/vsub.vi/...
-;; -------------------------------------------------------------------------
-
-(define_insn_and_split "<optab><mode>3"
- [(set (match_operand:VLSI 0 "register_operand")
- (any_int_binop_no_shift:VLSI
- (match_operand:VLSI 1 "<binop_rhs1_predicate>")
- (match_operand:VLSI 2 "<binop_rhs2_predicate>")))]
- "TARGET_VECTOR && can_create_pseudo_p ()"
- "#"
- "&& 1"
- [(const_int 0)]
-{
- riscv_vector::emit_vlmax_insn (code_for_pred (<CODE>, <MODE>mode),
- riscv_vector::BINARY_OP, operands);
- DONE;
-}
-[(set_attr "type" "vector")]
-)
-
-;; -------------------------------------------------------------------------
-;; ---- [FP] Binary operations
-;; -------------------------------------------------------------------------
-;; Includes:
-;; - vfadd.vv/vfsub.vv/vfmul.vv/vfdiv.vv
-;; - vfadd.vf/vfsub.vf/vfmul.vf/vfdiv.vf
-;; -------------------------------------------------------------------------
-(define_insn_and_split "<optab><mode>3"
- [(set (match_operand:VLSF 0 "register_operand")
- (any_float_binop:VLSF
- (match_operand:VLSF 1 "<binop_rhs1_predicate>")
- (match_operand:VLSF 2 "<binop_rhs2_predicate>")))]
- "TARGET_VECTOR && can_create_pseudo_p ()"
- "#"
- "&& 1"
- [(const_int 0)]
-{
- riscv_vector::emit_vlmax_insn (code_for_pred (<CODE>, <MODE>mode),
- riscv_vector::BINARY_OP_FRM_DYN, operands);
- DONE;
-}
-[(set_attr "type" "vector")]
-)
-
-;; -------------------------------------------------------------------------
-;; Includes:
-;; - vfmin.vv/vfmax.vv
-;; - vfmin.vf/vfmax.vf
-;; - fmax/fmaxf in math.h
-;; -------------------------------------------------------------------------
-(define_insn_and_split "<optab><mode>3"
- [(set (match_operand:VLSF 0 "register_operand")
- (any_float_binop_nofrm:VLSF
- (match_operand:VLSF 1 "<binop_rhs1_predicate>")
- (match_operand:VLSF 2 "<binop_rhs2_predicate>")))]
- "TARGET_VECTOR && can_create_pseudo_p ()"
- "#"
- "&& 1"
- [(const_int 0)]
-{
- riscv_vector::emit_vlmax_insn (code_for_pred (<CODE>, <MODE>mode),
- riscv_vector::BINARY_OP, operands);
- DONE;
-}
-[(set_attr "type" "vector")]
-)
-
-;; -------------------------------------------------------------------------
-;; Includes:
-;; - vfsgnj.vv
-;; - vfsgnj.vf
-;; -------------------------------------------------------------------------
-(define_insn_and_split "copysign<mode>3"
- [(set (match_operand:VLSF 0 "register_operand")
- (unspec:VLSF
- [(match_operand:VLSF 1 "register_operand")
- (match_operand:VLSF 2 "register_operand")] UNSPEC_VCOPYSIGN))]
- "TARGET_VECTOR && can_create_pseudo_p ()"
- "#"
- "&& 1"
- [(const_int 0)]
- {
- riscv_vector::emit_vlmax_insn (code_for_pred (UNSPEC_VCOPYSIGN, <MODE>mode),
- riscv_vector::BINARY_OP, operands);
- DONE;
- }
- [(set_attr "type" "vector")]
-)
-
-;; -------------------------------------------------------------------------
-;; Includes:
-;; - vfsgnjx.vv
-;; - vfsgnjx.vf
-;; -------------------------------------------------------------------------
-(define_insn_and_split "xorsign<mode>3"
- [(set (match_operand:VLSF 0 "register_operand")
- (unspec:VLSF
- [(match_operand:VLSF 1 "register_operand")
- (match_operand:VLSF 2 "register_operand")] UNSPEC_VXORSIGN))]
- "TARGET_VECTOR && can_create_pseudo_p ()"
- "#"
- "&& 1"
- [(const_int 0)]
- {
- riscv_vector::emit_vlmax_insn (code_for_pred (UNSPEC_VXORSIGN, <MODE>mode),
- riscv_vector::BINARY_OP, operands);
- DONE;
- }
-)
-
-;; -------------------------------------------------------------------------------
-;; ---- [INT] Unary operations
-;; -------------------------------------------------------------------------------
-;; Includes:
-;; - vneg.v/vnot.v
-;; -------------------------------------------------------------------------------
-
-(define_insn_and_split "<optab><mode>2"
- [(set (match_operand:VLSI 0 "register_operand")
- (any_int_unop:VLSI
- (match_operand:VLSI 1 "register_operand")))]
- "TARGET_VECTOR && can_create_pseudo_p ()"
- "#"
- "&& 1"
- [(const_int 0)]
-{
- insn_code icode = code_for_pred (<CODE>, <MODE>mode);
- riscv_vector::emit_vlmax_insn (icode, riscv_vector::UNARY_OP, operands);
- DONE;
-}
-[(set_attr "type" "vector")]
-)
diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
index aca86554a94..fe2405f6032 100644
--- a/gcc/config/riscv/autovec.md
+++ b/gcc/config/riscv/autovec.md
@@ -420,10 +420,10 @@
;; -------------------------------------------------------------------------
(define_insn_and_split "<optab><mode>3"
- [(set (match_operand:VI 0 "register_operand")
- (any_int_binop_no_shift:VI
- (match_operand:VI 1 "<binop_rhs1_predicate>")
- (match_operand:VI 2 "<binop_rhs2_predicate>")))]
+ [(set (match_operand:V_VLSI 0 "register_operand")
+ (any_int_binop_no_shift:V_VLSI
+ (match_operand:V_VLSI 1 "<binop_rhs1_predicate>")
+ (match_operand:V_VLSI 2 "<binop_rhs2_predicate>")))]
"TARGET_VECTOR && can_create_pseudo_p ()"
"#"
"&& 1"
@@ -985,9 +985,9 @@
;; - vneg.v/vnot.v
;; -------------------------------------------------------------------------------
(define_insn_and_split "<optab><mode>2"
- [(set (match_operand:VI 0 "register_operand")
- (any_int_unop:VI
- (match_operand:VI 1 "register_operand")))]
+ [(set (match_operand:V_VLSI 0 "register_operand")
+ (any_int_unop:V_VLSI
+ (match_operand:V_VLSI 1 "register_operand")))]
"TARGET_VECTOR && can_create_pseudo_p ()"
"#"
"&& 1"
@@ -1516,10 +1516,10 @@
;; - vfadd.vf/vfsub.vf/...
;; -------------------------------------------------------------------------
(define_insn_and_split "<optab><mode>3"
- [(set (match_operand:VF 0 "register_operand")
- (any_float_binop:VF
- (match_operand:VF 1 "register_operand")
- (match_operand:VF 2 "register_operand")))]
+ [(set (match_operand:V_VLSF 0 "register_operand")
+ (any_float_binop:V_VLSF
+ (match_operand:V_VLSF 1 "register_operand")
+ (match_operand:V_VLSF 2 "register_operand")))]
"TARGET_VECTOR && can_create_pseudo_p ()"
"#"
"&& 1"
@@ -1537,10 +1537,10 @@
;; - vfmin.vf/vfmax.vf
;; -------------------------------------------------------------------------
(define_insn_and_split "<optab><mode>3"
- [(set (match_operand:VF 0 "register_operand")
- (any_float_binop_nofrm:VF
- (match_operand:VF 1 "register_operand")
- (match_operand:VF 2 "register_operand")))]
+ [(set (match_operand:V_VLSF 0 "register_operand")
+ (any_float_binop_nofrm:V_VLSF
+ (match_operand:V_VLSF 1 "register_operand")
+ (match_operand:V_VLSF 2 "register_operand")))]
"TARGET_VECTOR && can_create_pseudo_p ()"
"#"
"&& 1"
@@ -1563,10 +1563,10 @@
;; Leave the pattern like this as to still allow combine to match
;; a negated copysign (see vector.md) before adding the UNSPEC_VPREDICATE later.
(define_insn_and_split "copysign<mode>3"
- [(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr")
- (unspec:VF
- [(match_operand:VF 1 "register_operand" " vr, vr, vr, vr")
- (match_operand:VF 2 "register_operand" " vr, vr, vr, vr")] UNSPEC_VCOPYSIGN))]
+ [(set (match_operand:V_VLSF 0 "register_operand" "=vd, vd, vr, vr")
+ (unspec:V_VLSF
+ [(match_operand:V_VLSF 1 "register_operand" " vr, vr, vr, vr")
+ (match_operand:V_VLSF 2 "register_operand" " vr, vr, vr, vr")] UNSPEC_VCOPYSIGN))]
"TARGET_VECTOR && can_create_pseudo_p ()"
"#"
"&& 1"
@@ -1585,9 +1585,9 @@
;; - vfsgnjx.vf
;; -------------------------------------------------------------------------------
(define_expand "xorsign<mode>3"
- [(match_operand:VF 0 "register_operand")
- (match_operand:VF 1 "register_operand")
- (match_operand:VF 2 "register_operand")]
+ [(match_operand:V_VLSF 0 "register_operand")
+ (match_operand:V_VLSF 1 "register_operand")
+ (match_operand:V_VLSF 2 "register_operand")]
"TARGET_VECTOR"
{
riscv_vector::emit_vlmax_insn (code_for_pred (UNSPEC_VXORSIGN, <MODE>mode),
reply other threads:[~2023-09-18 18:27 UTC|newest]
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