[gcc(refs/vendors/riscv/heads/gcc-13-with-riscv-opts)] RISC-V: Removed misleading comments in testcases

[Jeff Law <law@gcc.gnu.org>]

https://gcc.gnu.org/g:5c5245a094f8fbf6a9edcb069d46f1a493d1ae12

commit 5c5245a094f8fbf6a9edcb069d46f1a493d1ae12
Author: Lehua Ding <lehua.ding@rivai.ai>
Date:   Mon Sep 18 20:24:26 2023 +0800

    RISC-V: Removed misleading comments in testcases
    
    This patch removed the misleading comments in testcases since we
    support fold min(int, poly) to constant by this patch
    (https://gcc.gnu.org/pipermail/gcc-patches/2023-September/629651.html).
    Thereby the csrr will not appear inside the assembly code, even if there
    is no support for some VLS vector patterns.
    
    gcc/testsuite/ChangeLog:
    
            * gcc.target/riscv/rvv/autovec/vls/div-1.c: Removed comments.
            * gcc.target/riscv/rvv/autovec/vls/shift-3.c: Ditto.
    
    (cherry picked from commit 1b03c73295266984378dd9da99a9458b591b964c)

Diff:
---
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/div-1.c   | 1 -
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/shift-3.c | 1 -
 2 files changed, 2 deletions(-)

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/div-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/div-1.c
index 40224c69458..e36fa9decfd 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/div-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/div-1.c
@@ -54,5 +54,4 @@ DEF_OP_VV (div, 256, int64_t, /)
 DEF_OP_VV (div, 512, int64_t, /)
 
 /* { dg-final { scan-assembler-times {vdivu?\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 42 } } */
-/* TODO: Ideally, we should make sure there is no "csrr vlenb". However, we still have 'csrr vlenb' for some cases since we don't support VLS mode conversion which are needed by division.  */
 /* { dg-final { scan-assembler-not {csrr} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/shift-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/shift-3.c
index b34a349949b..db2295b2dd6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/shift-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/shift-3.c
@@ -54,5 +54,4 @@ DEF_OP_VV (shift, 256, int64_t, <<)
 DEF_OP_VV (shift, 512, int64_t, <<)
 
 /* { dg-final { scan-assembler-times {vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 41 } } */
-/* TODO: Ideally, we should make sure there is no "csrr vlenb". However, we still have 'csrr vlenb' for some cases since we don't support VLS mode conversion which are needed by division.  */
 /* { dg-final { scan-assembler-not {csrr} } } */