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From: Lehua Ding <lhtin@gcc.gnu.org>
To: gcc-cvs@gcc.gnu.org
Subject: [gcc r14-4174] RISC-V: Support VLS floating-point extend/truncate
Date: Wed, 20 Sep 2023 12:40:07 +0000 (GMT) [thread overview]
Message-ID: <20230920124007.E11043858422@sourceware.org> (raw)
https://gcc.gnu.org/g:b34397857adb7b3ae72e2701879bcb4e19165d63
commit r14-4174-gb34397857adb7b3ae72e2701879bcb4e19165d63
Author: Juzhe-Zhong <juzhe.zhong@rivai.ai>
Date: Wed Sep 20 19:51:19 2023 +0800
RISC-V: Support VLS floating-point extend/truncate
Regression passed.
Committed.
gcc/ChangeLog:
* config/riscv/vector-iterators.md: Extend VLS floating-point.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/widen/widen-10.c: Adapt test.
* gcc.target/riscv/rvv/autovec/widen/widen-11.c: Ditto.
* gcc.target/riscv/rvv/autovec/widen/widen-12.c: Ditto.
* gcc.target/riscv/rvv/autovec/widen/widen-complicate-7.c: Ditto.
* gcc.target/riscv/rvv/autovec/widen/widen-complicate-8.c: Ditto.
* gcc.target/riscv/rvv/autovec/widen/widen-complicate-9.c: Ditto.
* gcc.target/riscv/rvv/autovec/vls/ext-4.c: New test.
* gcc.target/riscv/rvv/autovec/vls/ext-5.c: New test.
* gcc.target/riscv/rvv/autovec/vls/trunc-4.c: New test.
* gcc.target/riscv/rvv/autovec/vls/trunc-5.c: New test.
Diff:
---
gcc/config/riscv/vector-iterators.md | 95 ++++++++++++++++++++++
.../gcc.target/riscv/rvv/autovec/vls/ext-4.c | 35 ++++++++
.../gcc.target/riscv/rvv/autovec/vls/ext-5.c | 27 ++++++
.../gcc.target/riscv/rvv/autovec/vls/trunc-4.c | 35 ++++++++
.../gcc.target/riscv/rvv/autovec/vls/trunc-5.c | 27 ++++++
.../gcc.target/riscv/rvv/autovec/widen/widen-10.c | 2 +-
.../gcc.target/riscv/rvv/autovec/widen/widen-11.c | 2 +-
.../gcc.target/riscv/rvv/autovec/widen/widen-12.c | 2 +-
.../riscv/rvv/autovec/widen/widen-complicate-7.c | 2 +-
.../riscv/rvv/autovec/widen/widen-complicate-8.c | 2 +-
.../riscv/rvv/autovec/widen/widen-complicate-9.c | 2 +-
11 files changed, 225 insertions(+), 6 deletions(-)
diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md
index 73df55a69c8..053d84c0c7d 100644
--- a/gcc/config/riscv/vector-iterators.md
+++ b/gcc/config/riscv/vector-iterators.md
@@ -994,6 +994,28 @@
(RVVM8DF "TARGET_VECTOR_ELEN_FP_64") (RVVM4DF "TARGET_VECTOR_ELEN_FP_64")
(RVVM2DF "TARGET_VECTOR_ELEN_FP_64") (RVVM1DF "TARGET_VECTOR_ELEN_FP_64")
+
+ (V1SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32")
+ (V2SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32")
+ (V4SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32")
+ (V8SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32")
+ (V16SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 64")
+ (V32SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128")
+ (V64SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 256")
+ (V128SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 512")
+ (V256SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 1024")
+ (V512SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 2048")
+ (V1024SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 4096")
+ (V1DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64")
+ (V2DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64")
+ (V4DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64")
+ (V8DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 64")
+ (V16DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 128")
+ (V32DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 256")
+ (V64DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 512")
+ (V128DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 1024")
+ (V256DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 2048")
+ (V512DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 4096")
])
(define_mode_iterator VWEXTF [
@@ -1049,6 +1071,17 @@
(define_mode_iterator VQEXTF [
(RVVM8DF "TARGET_VECTOR_ELEN_FP_64") (RVVM4DF "TARGET_VECTOR_ELEN_FP_64")
(RVVM2DF "TARGET_VECTOR_ELEN_FP_64") (RVVM1DF "TARGET_VECTOR_ELEN_FP_64")
+
+ (V1DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64")
+ (V2DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64")
+ (V4DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64")
+ (V8DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 64")
+ (V16DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 128")
+ (V32DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 256")
+ (V64DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 512")
+ (V128DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 1024")
+ (V256DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 2048")
+ (V512DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 4096")
])
(define_mode_iterator VOEXTI [
@@ -2343,6 +2376,27 @@
(V128DI "V128SI")
(V256DI "V256SI")
(V512DI "V512SI")
+ (V1SF "V1HF")
+ (V2SF "V2HF")
+ (V4SF "V4HF")
+ (V8SF "V8HF")
+ (V16SF "V16HF")
+ (V32SF "V32HF")
+ (V64SF "V64HF")
+ (V128SF "V128HF")
+ (V256SF "V256HF")
+ (V512SF "V512HF")
+ (V1024SF "V1024HF")
+ (V1DF "V1SF")
+ (V2DF "V2SF")
+ (V4DF "V4SF")
+ (V8DF "V8SF")
+ (V16DF "V16SF")
+ (V32DF "V32SF")
+ (V64DF "V64SF")
+ (V128DF "V128SF")
+ (V256DF "V256SF")
+ (V512DF "V512SF")
])
(define_mode_attr V_QUAD_TRUNC [
@@ -2373,6 +2427,16 @@
(V128DI "V128HI")
(V256DI "V256HI")
(V512DI "V512HI")
+ (V1DF "V1HF")
+ (V2DF "V2HF")
+ (V4DF "V4HF")
+ (V8DF "V8HF")
+ (V16DF "V16HF")
+ (V32DF "V32HF")
+ (V64DF "V64HF")
+ (V128DF "V128HF")
+ (V256DF "V256HF")
+ (V512DF "V512HF")
])
(define_mode_attr V_OCT_TRUNC [
@@ -2435,6 +2499,27 @@
(V128DI "v128si")
(V256DI "v256si")
(V512DI "v512si")
+ (V1SF "v1hf")
+ (V2SF "v2hf")
+ (V4SF "v4hf")
+ (V8SF "v8hf")
+ (V16SF "v16hf")
+ (V32SF "v32hf")
+ (V64SF "v64hf")
+ (V128SF "v128hf")
+ (V256SF "v256hf")
+ (V512SF "v512hf")
+ (V1024SF "v1024hf")
+ (V1DF "v1sf")
+ (V2DF "v2sf")
+ (V4DF "v4sf")
+ (V8DF "v8sf")
+ (V16DF "v16sf")
+ (V32DF "v32sf")
+ (V64DF "v64sf")
+ (V128DF "v128sf")
+ (V256DF "v256sf")
+ (V512DF "v512sf")
])
(define_mode_attr v_quad_trunc [
@@ -2465,6 +2550,16 @@
(V128DI "v128hi")
(V256DI "v256hi")
(V512DI "v512hi")
+ (V1DF "v1hf")
+ (V2DF "v2hf")
+ (V4DF "v4hf")
+ (V8DF "v8hf")
+ (V16DF "v16hf")
+ (V32DF "v32hf")
+ (V64DF "v64hf")
+ (V128DF "v128hf")
+ (V256DF "v256hf")
+ (V512DF "v512hf")
])
(define_mode_attr v_oct_trunc [
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/ext-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/ext-4.c
new file mode 100644
index 00000000000..7593a35d666
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/ext-4.c
@@ -0,0 +1,35 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+
+#include "def.h"
+
+DEF_CONVERT (fwcvt, _Float16, float, 4)
+DEF_CONVERT (fwcvt, _Float16, float, 16)
+DEF_CONVERT (fwcvt, _Float16, float, 32)
+DEF_CONVERT (fwcvt, _Float16, float, 64)
+DEF_CONVERT (fwcvt, _Float16, float, 128)
+DEF_CONVERT (fwcvt, _Float16, float, 256)
+DEF_CONVERT (fwcvt, _Float16, float, 512)
+DEF_CONVERT (fwcvt, _Float16, float, 1024)
+
+DEF_CONVERT (fwcvt, float, double, 4)
+DEF_CONVERT (fwcvt, float, double, 16)
+DEF_CONVERT (fwcvt, float, double, 32)
+DEF_CONVERT (fwcvt, float, double, 64)
+DEF_CONVERT (fwcvt, float, double, 128)
+DEF_CONVERT (fwcvt, float, double, 256)
+
+/* { dg-final { scan-assembler-times {vfwcvt\.f\.f\.v} 14 } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
+/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/ext-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/ext-5.c
new file mode 100644
index 00000000000..5dca5a7875d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/ext-5.c
@@ -0,0 +1,27 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+
+#include "def.h"
+
+DEF_CONVERT (fwcvt, _Float16, double, 4)
+DEF_CONVERT (fwcvt, _Float16, double, 16)
+DEF_CONVERT (fwcvt, _Float16, double, 32)
+DEF_CONVERT (fwcvt, _Float16, double, 64)
+DEF_CONVERT (fwcvt, _Float16, double, 128)
+DEF_CONVERT (fwcvt, _Float16, double, 256)
+DEF_CONVERT (fwcvt, _Float16, double, 512)
+
+/* { dg-final { scan-assembler-times {vfwcvt\.f\.f\.v} 14 } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
+/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/trunc-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/trunc-4.c
new file mode 100644
index 00000000000..d9a5eeb212e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/trunc-4.c
@@ -0,0 +1,35 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+
+#include "def.h"
+
+DEF_CONVERT (fncvt, float, _Float16, 4)
+DEF_CONVERT (fncvt, float, _Float16, 16)
+DEF_CONVERT (fncvt, float, _Float16, 32)
+DEF_CONVERT (fncvt, float, _Float16, 64)
+DEF_CONVERT (fncvt, float, _Float16, 128)
+DEF_CONVERT (fncvt, float, _Float16, 256)
+DEF_CONVERT (fncvt, float, _Float16, 512)
+DEF_CONVERT (fncvt, float, _Float16, 1024)
+
+DEF_CONVERT (fncvt, double, float, 4)
+DEF_CONVERT (fncvt, double, float, 16)
+DEF_CONVERT (fncvt, double, float, 32)
+DEF_CONVERT (fncvt, double, float, 64)
+DEF_CONVERT (fncvt, double, float, 128)
+DEF_CONVERT (fncvt, double, float, 256)
+
+/* { dg-final { scan-assembler-times {vfncvt\.f\.f\.w} 14 } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
+/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/trunc-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/trunc-5.c
new file mode 100644
index 00000000000..b87a5c4dfad
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/trunc-5.c
@@ -0,0 +1,27 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+
+#include "def.h"
+
+DEF_CONVERT (fncvt, double, _Float16, 4)
+DEF_CONVERT (fncvt, double, _Float16, 16)
+DEF_CONVERT (fncvt, double, _Float16, 32)
+DEF_CONVERT (fncvt, double, _Float16, 64)
+DEF_CONVERT (fncvt, double, _Float16, 128)
+DEF_CONVERT (fncvt, double, _Float16, 256)
+DEF_CONVERT (fncvt, double, _Float16, 512)
+
+/* { dg-final { scan-assembler-times {vfncvt} 14 } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
+/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-10.c
index 490f1a41068..28aacb95904 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-10.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-10.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -O3 -ffast-math" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -O3 -ffast-math -fno-vect-cost-model" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-11.c
index 4d44a40fed3..6d39bffbdc7 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-11.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-11.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -O3 -ffast-math" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -O3 -ffast-math -fno-vect-cost-model" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-12.c
index 2cb2a1edebf..1f50fd24ae4 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-12.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-12.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -O3 -ffast-math" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -O3 -ffast-math -fno-vect-cost-model" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-7.c
index 2e3f6664d93..5d93a0ed60a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-7.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-8.c
index 2acfbd01c6d..1a496bcfcea 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-8.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-9.c
index da7f870c12b..4d2f7ccab99 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-9.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */
#include <stdint-gcc.h>
reply other threads:[~2023-09-20 12:40 UTC|newest]
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