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From: Pan Li <panli@gcc.gnu.org> To: gcc-cvs@gcc.gnu.org Subject: [gcc r14-4175] RISC-V: Support simplifying x/(-1) to neg for vector. Date: Wed, 20 Sep 2023 13:50:33 +0000 (GMT) [thread overview] Message-ID: <20230920135033.B1D503857835@sourceware.org> (raw) https://gcc.gnu.org/g:b9cb735fc1bb4ca2339ab900e2d07667d7c0f6b4 commit r14-4175-gb9cb735fc1bb4ca2339ab900e2d07667d7c0f6b4 Author: Yanzhang Wang <yanzhang.wang@intel.com> Date: Wed Sep 20 11:36:20 2023 +0800 RISC-V: Support simplifying x/(-1) to neg for vector. gcc/ChangeLog: * simplify-rtx.cc (simplify_context::simplify_binary_operation_1): support simplifying vector int not only scalar int. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/simplify-vdiv.c: New test. Signed-off-by: Yanzhang Wang <yanzhang.wang@intel.com> Diff: --- gcc/simplify-rtx.cc | 4 ++-- .../gcc.target/riscv/rvv/base/simplify-vdiv.c | 18 ++++++++++++++++++ 2 files changed, 20 insertions(+), 2 deletions(-) diff --git a/gcc/simplify-rtx.cc b/gcc/simplify-rtx.cc index eb1ac120832..170406aa28b 100644 --- a/gcc/simplify-rtx.cc +++ b/gcc/simplify-rtx.cc @@ -4093,7 +4093,7 @@ simplify_context::simplify_binary_operation_1 (rtx_code code, } } } - else if (SCALAR_INT_MODE_P (mode)) + else if (SCALAR_INT_MODE_P (mode) || GET_MODE_CLASS (mode) == MODE_VECTOR_INT) { /* 0/x is 0 (or x&0 if x has side-effects). */ if (trueop0 == CONST0_RTX (mode) @@ -4111,7 +4111,7 @@ simplify_context::simplify_binary_operation_1 (rtx_code code, return tem; } /* x/-1 is -x. */ - if (trueop1 == constm1_rtx) + if (trueop1 == CONSTM1_RTX (mode)) { rtx x = rtl_hooks.gen_lowpart_no_emit (mode, op0); if (x) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/simplify-vdiv.c b/gcc/testsuite/gcc.target/riscv/rvv/base/simplify-vdiv.c new file mode 100644 index 00000000000..08300061832 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/simplify-vdiv.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */ + +#include "riscv_vector.h" + +#define VDIV_WITH_LMUL(LMUL, DTYPE) \ + vint##DTYPE##m##LMUL##_t \ + shortcut_for_riscv_vdiv_case_##LMUL##_##DTYPE \ + (vint##DTYPE##m##LMUL##_t v1, \ + size_t vl) \ + { \ + return __riscv_vdiv_vx_i##DTYPE##m##LMUL (v1, -1, vl); \ + } + +VDIV_WITH_LMUL (1, 16) +VDIV_WITH_LMUL (1, 32) + +/* { dg-final { scan-assembler-times {vneg\.v} 2 } } */
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