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From: Michael Meissner <meissner@gcc.gnu.org> To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/users/meissner/heads/work134-vpair)] Adjust vector pair split functions. Date: Mon, 25 Sep 2023 16:55:43 +0000 (GMT) [thread overview] Message-ID: <20230925165543.6E5E23858028@sourceware.org> (raw) https://gcc.gnu.org/g:e869b36d7ce79a44d87bdd4233dde66a22842586 commit e869b36d7ce79a44d87bdd4233dde66a22842586 Author: Michael Meissner <meissner@linux.ibm.com> Date: Mon Sep 25 12:55:23 2023 -0400 Adjust vector pair split functions. 2023-09-21 Michael Meissner <meissner@linux.ibm.com> gcc/ * config/rs6000/rs6000.cc (split_unary_vector_pair): Add code to allow split to be done before register allocation time. (split_binary_vector_pair): Likewise. (split_fma_vector_pair): Likewise. * config/rs6000/vector-pair.md (vpair_get_vector_<vp_pmode>): Add code to allow split to be done before register allocation time. Diff: --- gcc/config/rs6000/rs6000.cc | 65 ++++++++++++++++++++++------------------ gcc/config/rs6000/vector-pair.md | 15 +++++----- 2 files changed, 44 insertions(+), 36 deletions(-) diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc index 7a16a686d4b..936b6135874 100644 --- a/gcc/config/rs6000/rs6000.cc +++ b/gcc/config/rs6000/rs6000.cc @@ -27192,15 +27192,17 @@ split_unary_vector_pair (machine_mode mode, /* vector mode. */ rtx operands[], /* dest, src. */ rtx (*func)(rtx, rtx)) /* create insn. */ { - unsigned reg0 = reg_or_subregno (operands[0]); - unsigned reg1 = reg_or_subregno (operands[1]); + rtx op0 = operands[0]; + rtx op1 = operands[1]; + machine_mode orig_mode = GET_MODE (op0); - emit_insn (func (gen_rtx_REG (mode, reg0), - gen_rtx_REG (mode, reg1))); - - emit_insn (func (gen_rtx_REG (mode, reg0 + 1), - gen_rtx_REG (mode, reg1 + 1))); + rtx reg0_vector0 = simplify_gen_subreg (mode, op0, orig_mode, 0); + rtx reg1_vector0 = simplify_gen_subreg (mode, op1, orig_mode, 0); + rtx reg0_vector1 = simplify_gen_subreg (mode, op0, orig_mode, 16); + rtx reg1_vector1 = simplify_gen_subreg (mode, op1, orig_mode, 16); + emit_insn (func (reg0_vector0, reg1_vector0)); + emit_insn (func (reg0_vector1, reg1_vector1)); return; } @@ -27211,18 +27213,20 @@ split_binary_vector_pair (machine_mode mode, /* vector mode. */ rtx operands[], /* dest, src. */ rtx (*func)(rtx, rtx, rtx)) /* create insn. */ { - unsigned reg0 = reg_or_subregno (operands[0]); - unsigned reg1 = reg_or_subregno (operands[1]); - unsigned reg2 = reg_or_subregno (operands[2]); - - emit_insn (func (gen_rtx_REG (mode, reg0), - gen_rtx_REG (mode, reg1), - gen_rtx_REG (mode, reg2))); + rtx op0 = operands[0]; + rtx op1 = operands[1]; + rtx op2 = operands[2]; + machine_mode orig_mode = GET_MODE (op0); - emit_insn (func (gen_rtx_REG (mode, reg0 + 1), - gen_rtx_REG (mode, reg1 + 1), - gen_rtx_REG (mode, reg2 + 1))); + rtx reg0_vector0 = simplify_gen_subreg (mode, op0, orig_mode, 0); + rtx reg1_vector0 = simplify_gen_subreg (mode, op1, orig_mode, 0); + rtx reg2_vector0 = simplify_gen_subreg (mode, op2, orig_mode, 0); + rtx reg0_vector1 = simplify_gen_subreg (mode, op0, orig_mode, 16); + rtx reg1_vector1 = simplify_gen_subreg (mode, op1, orig_mode, 16); + rtx reg2_vector1 = simplify_gen_subreg (mode, op2, orig_mode, 16); + emit_insn (func (reg0_vector0, reg1_vector0, reg2_vector0)); + emit_insn (func (reg0_vector1, reg1_vector1, reg2_vector1)); return; } @@ -27234,21 +27238,24 @@ split_fma_vector_pair (machine_mode mode, /* vector mode. */ rtx operands[], /* dest, src. */ rtx (*func)(rtx, rtx, rtx, rtx)) /* create insn. */ { - unsigned reg0 = reg_or_subregno (operands[0]); - unsigned reg1 = reg_or_subregno (operands[1]); - unsigned reg2 = reg_or_subregno (operands[2]); - unsigned reg3 = reg_or_subregno (operands[3]); + rtx op0 = operands[0]; + rtx op1 = operands[1]; + rtx op2 = operands[2]; + rtx op3 = operands[3]; + machine_mode orig_mode = GET_MODE (op0); - emit_insn (func (gen_rtx_REG (mode, reg0), - gen_rtx_REG (mode, reg1), - gen_rtx_REG (mode, reg2), - gen_rtx_REG (mode, reg3))); + rtx reg0_vector0 = simplify_gen_subreg (mode, op0, orig_mode, 0); + rtx reg1_vector0 = simplify_gen_subreg (mode, op1, orig_mode, 0); + rtx reg2_vector0 = simplify_gen_subreg (mode, op2, orig_mode, 0); + rtx reg3_vector0 = simplify_gen_subreg (mode, op3, orig_mode, 0); - emit_insn (func (gen_rtx_REG (mode, reg0 + 1), - gen_rtx_REG (mode, reg1 + 1), - gen_rtx_REG (mode, reg2 + 1), - gen_rtx_REG (mode, reg3 + 1))); + rtx reg0_vector1 = simplify_gen_subreg (mode, op0, orig_mode, 16); + rtx reg1_vector1 = simplify_gen_subreg (mode, op1, orig_mode, 16); + rtx reg2_vector1 = simplify_gen_subreg (mode, op2, orig_mode, 16); + rtx reg3_vector1 = simplify_gen_subreg (mode, op3, orig_mode, 16); + emit_insn (func (reg0_vector0, reg1_vector0, reg2_vector0, reg3_vector0)); + emit_insn (func (reg0_vector1, reg1_vector1, reg2_vector1, reg3_vector1)); return; } diff --git a/gcc/config/rs6000/vector-pair.md b/gcc/config/rs6000/vector-pair.md index ddb38df51af..4d422f5a697 100644 --- a/gcc/config/rs6000/vector-pair.md +++ b/gcc/config/rs6000/vector-pair.md @@ -166,12 +166,13 @@ [(set (match_dup 1) (match_dup 3)) (set (match_dup 2) (match_dup 3))] { - unsigned reg0 = reg_or_subregno (operands[0]); - rtvec vec_zero = gen_rtvec (2, const0_rtx, const0_rtx); + rtx op0 = operands[0]; + unsigned offset_hi = (WORDS_BIG_ENDIAN) ? 0 : 16; + unsigned offset_lo = (WORDS_BIG_ENDIAN) ? 16 : 0; - operands[1] = gen_rtx_REG (V2DImode, reg0); - operands[2] = gen_rtx_REG (V2DImode, reg0 + 1); - operands[3] = gen_rtx_CONST_VECTOR (V2DImode, vec_zero); + operands[1] = simplify_gen_subreg (V2DImode, op0, OOmode, offset_hi); + operands[2] = simplify_gen_subreg (V2DImode, op0, OOmode, offset_lo); + operands[3] = CONST0_RTX (V2DImode); } [(set_attr "length" "8")]) @@ -213,12 +214,12 @@ "&& reload_completed" [(set (match_dup 0) (match_dup 3))] { - unsigned reg1 = reg_or_subregno (operands[1]); + machine_mode vmode = <VP_VEC_MODE>mode; unsigned reg_num = UINTVAL (operands[2]); if (!WORDS_BIG_ENDIAN) reg_num = 1 - reg_num; - operands[3] = gen_rtx_REG (<VP_VEC_MODE>mode, reg1 + reg_num); + operands[3] = simplify_gen_subreg (vmode, operands[0], OOmode, reg_num * 16); }) ;; Optimize extracting an 128-bit vector from a vector pair in memory.
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