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From: Jeff Law <law@gcc.gnu.org>
To: gcc-cvs@gcc.gnu.org
Subject: [gcc(refs/vendors/riscv/heads/gcc-13-with-riscv-opts)] RISC-V: Bugfix for scalar move with merged operand
Date: Tue, 26 Sep 2023 15:09:16 +0000 (GMT)	[thread overview]
Message-ID: <20230926150916.ACAE23858412@sourceware.org> (raw)

https://gcc.gnu.org/g:f30cbc9659a83ae4b305ffe11964ca5c2a9b7d2a

commit f30cbc9659a83ae4b305ffe11964ca5c2a9b7d2a
Author: Pan Li <pan2.li@intel.com>
Date:   Sun Sep 17 15:16:47 2023 +0800

    RISC-V: Bugfix for scalar move with merged operand
    
    Given below example for VLS mode
    
    void
    test (vl_t *u)
    {
      vl_t t;
      long long *p = (long long *)&t;
    
      p[0] = p[1] = 2;
    
      *u = t;
    }
    
    The vec_set will simplify the insn to vmv.s.x when index is 0, without
    merged operand. That will result in some problems in DCE, aka:
    
    1:  137[DI] = a0
    2:  138[V2DI] = 134[V2DI]                              // deleted by DCE
    3:  139[DI] = #2                                       // deleted by DCE
    4:  140[DI] = #2                                       // deleted by DCE
    5:  141[V2DI] = vec_dup:V2DI (139[DI])                 // deleted by DCE
    6:  138[V2DI] = vslideup_imm (138[V2DI], 141[V2DI], 1) // deleted by DCE
    7:  135[V2DI] = 138[V2DI]                              // deleted by DCE
    8:  142[V2DI] = 135[V2DI]                              // deleted by DCE
    9:  143[DI] = #2
    10: 142[V2DI] = vec_dup:V2DI (143[DI])
    11: (137[DI]) = 142[V2DI]
    
    The higher 64 bits of 142[V2DI] is unknown here and it generated incorrect
    code when store back to memory. This patch would like to fix this issue
    by adding a new SCALAR_MOVE_MERGED_OP for vec_set.
    
    Please note this patch doesn't enable VLS for vec_set, the underlying
    patches will support this soon.
    
    gcc/ChangeLog:
    
            * config/riscv/autovec.md: Bugfix.
            * config/riscv/riscv-protos.h (SCALAR_MOVE_MERGED_OP): New enum.
    
    gcc/testsuite/ChangeLog:
    
            * gcc.target/riscv/rvv/base/scalar-move-merged-run-1.c: New test.
    
    Signed-off-by: Pan Li <pan2.li@intel.com>
    (cherry picked from commit 28f16f6d9b4fc1391275f4ba24dc2019ee64fc22)

Diff:
---
 gcc/config/riscv/autovec.md                        |  4 +--
 gcc/config/riscv/riscv-protos.h                    |  4 +++
 .../riscv/rvv/base/scalar-move-merged-run-1.c      | 29 ++++++++++++++++++++++
 3 files changed, 35 insertions(+), 2 deletions(-)

diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
index 493d5745485..f6d8616d5a2 100644
--- a/gcc/config/riscv/autovec.md
+++ b/gcc/config/riscv/autovec.md
@@ -1401,9 +1401,9 @@
   /* If we set the first element, emit an v(f)mv.s.[xf].  */
   if (operands[2] == const0_rtx)
     {
-      rtx ops[] = {operands[0], operands[1]};
+      rtx ops[] = {operands[0], operands[0], operands[1]};
       riscv_vector::emit_nonvlmax_insn (code_for_pred_broadcast (<MODE>mode),
-                                         riscv_vector::SCALAR_MOVE_OP, ops, CONST1_RTX (Pmode));
+					riscv_vector::SCALAR_MOVE_MERGED_OP, ops, CONST1_RTX (Pmode));
     }
   else
     {
diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
index 5a2d218d67b..6d9367d9602 100644
--- a/gcc/config/riscv/riscv-protos.h
+++ b/gcc/config/riscv/riscv-protos.h
@@ -345,6 +345,10 @@ enum insn_type : unsigned int
   SCALAR_MOVE_OP = HAS_DEST_P | HAS_MASK_P | USE_ONE_TRUE_MASK_P | HAS_MERGE_P
 		   | USE_VUNDEF_MERGE_P | TDEFAULT_POLICY_P | MDEFAULT_POLICY_P
 		   | UNARY_OP_P,
+
+  SCALAR_MOVE_MERGED_OP = HAS_DEST_P | HAS_MASK_P | USE_ONE_TRUE_MASK_P
+			  | HAS_MERGE_P | TDEFAULT_POLICY_P | MDEFAULT_POLICY_P
+			  | UNARY_OP_P,
 };
 
 enum vlmul_type
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/scalar-move-merged-run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/scalar-move-merged-run-1.c
new file mode 100644
index 00000000000..7aee75c6940
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/scalar-move-merged-run-1.c
@@ -0,0 +1,29 @@
+/* { dg-do run { target { riscv_vector } } } */
+/* { dg-options "-O3 -Wno-psabi" } */
+
+#define TEST_VAL 2
+
+typedef long long vl_t __attribute__((vector_size(2 * sizeof (long long))));
+
+void init_vl (vl_t *u)
+{
+  vl_t t;
+  long long *p = (long long *)&t;
+
+  p[0] = p[1] = TEST_VAL;
+
+  *u = t;
+}
+
+int
+main ()
+{
+  vl_t vl = {};
+
+  init_vl (&vl);
+
+  if (vl[0] != TEST_VAL || vl[1] != TEST_VAL)
+    __builtin_abort ();
+
+  return 0;
+}

                 reply	other threads:[~2023-09-26 15:09 UTC|newest]

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