From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 2119) id 2C1E7385C6F2; Tue, 26 Sep 2023 15:09:47 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 2C1E7385C6F2 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1695740987; bh=9cxy+PqCs81eMgaZ/d6m/UZY/viE1SxaO/DU+dx4300=; h=From:To:Subject:Date:From; b=HllzfazLMoBr1tTLV3Rs2SBsLShQXjY7H5Oze0LfwrGezQCUfqXoRUwVrYEfUbUXW w3v8myoVFuIK9av9O5ak9GTawrVSUExsT4R9Z8kFkGw5dLEYJWSGb+phvbdMl2GJrR i9fkW3rGiSpXB5pf/JJASA+TTNjOJxD+h/fFHYAE= Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Jeff Law To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/vendors/riscv/heads/gcc-13-with-riscv-opts)] RISC-V: Support VLS floating-point FMA/FNMA/FMS auto-vectorization X-Act-Checkin: gcc X-Git-Author: Juzhe-Zhong X-Git-Refname: refs/vendors/riscv/heads/gcc-13-with-riscv-opts X-Git-Oldrev: 110488c130cd49cc4707ce0c98d599bf1aaab418 X-Git-Newrev: 42510dcebefd8920e0831c6b6c846713af39a460 Message-Id: <20230926150947.2C1E7385C6F2@sourceware.org> Date: Tue, 26 Sep 2023 15:09:47 +0000 (GMT) List-Id: https://gcc.gnu.org/g:42510dcebefd8920e0831c6b6c846713af39a460 commit 42510dcebefd8920e0831c6b6c846713af39a460 Author: Juzhe-Zhong Date: Tue Sep 19 17:19:09 2023 +0800 RISC-V: Support VLS floating-point FMA/FNMA/FMS auto-vectorization Support VLS floating-point FMA/FNMA/FMS patterns. Regression no difference after this patch, Committed. gcc/ChangeLog: * config/riscv/autovec.md: Extend VLS floating-point modes. * config/riscv/vector.md: Ditto. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/vls/def.h: Add FMS tests. * gcc.target/riscv/rvv/autovec/vls/fma-5.c: New test. * gcc.target/riscv/rvv/autovec/vls/fma-6.c: New test. * gcc.target/riscv/rvv/autovec/vls/fma-7.c: New test. * gcc.target/riscv/rvv/autovec/vls/fms-1.c: New test. * gcc.target/riscv/rvv/autovec/vls/fms-2.c: New test. * gcc.target/riscv/rvv/autovec/vls/fms-3.c: New test. * gcc.target/riscv/rvv/autovec/vls/fnma-5.c: New test. * gcc.target/riscv/rvv/autovec/vls/fnma-6.c: New test. * gcc.target/riscv/rvv/autovec/vls/fnma-7.c: New test. (cherry picked from commit 28569e79e34ac8760833640abcb21c5b36add2b3) Diff: --- gcc/config/riscv/autovec.md | 50 ++--- gcc/config/riscv/vector.md | 222 ++++++++++----------- .../gcc.target/riscv/rvv/autovec/vls/def.h | 9 + .../gcc.target/riscv/rvv/autovec/vls/fma-5.c | 31 +++ .../gcc.target/riscv/rvv/autovec/vls/fma-6.c | 30 +++ .../gcc.target/riscv/rvv/autovec/vls/fma-7.c | 29 +++ .../gcc.target/riscv/rvv/autovec/vls/fms-1.c | 31 +++ .../gcc.target/riscv/rvv/autovec/vls/fms-2.c | 30 +++ .../gcc.target/riscv/rvv/autovec/vls/fms-3.c | 29 +++ .../gcc.target/riscv/rvv/autovec/vls/fnma-5.c | 31 +++ .../gcc.target/riscv/rvv/autovec/vls/fnma-6.c | 30 +++ .../gcc.target/riscv/rvv/autovec/vls/fnma-7.c | 29 +++ 12 files changed, 415 insertions(+), 136 deletions(-) diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md index 1aadb6eea1f..769ef6daa36 100644 --- a/gcc/config/riscv/autovec.md +++ b/gcc/config/riscv/autovec.md @@ -1135,12 +1135,12 @@ ;; ------------------------------------------------------------------------- (define_insn_and_split "fma4" - [(set (match_operand:VF 0 "register_operand") - (plus:VF - (mult:VF - (match_operand:VF 1 "register_operand") - (match_operand:VF 2 "register_operand")) - (match_operand:VF 3 "register_operand")))] + [(set (match_operand:V_VLSF 0 "register_operand") + (plus:V_VLSF + (mult:V_VLSF + (match_operand:V_VLSF 1 "register_operand") + (match_operand:V_VLSF 2 "register_operand")) + (match_operand:V_VLSF 3 "register_operand")))] "TARGET_VECTOR && can_create_pseudo_p ()" "#" "&& 1" @@ -1163,12 +1163,12 @@ ;; ------------------------------------------------------------------------- (define_insn_and_split "fnma4" - [(set (match_operand:VF 0 "register_operand") - (minus:VF - (match_operand:VF 3 "register_operand") - (mult:VF - (match_operand:VF 1 "register_operand") - (match_operand:VF 2 "register_operand"))))] + [(set (match_operand:V_VLSF 0 "register_operand") + (minus:V_VLSF + (match_operand:V_VLSF 3 "register_operand") + (mult:V_VLSF + (match_operand:V_VLSF 1 "register_operand") + (match_operand:V_VLSF 2 "register_operand"))))] "TARGET_VECTOR && can_create_pseudo_p ()" "#" "&& 1" @@ -1191,12 +1191,12 @@ ;; ------------------------------------------------------------------------- (define_insn_and_split "fms4" - [(set (match_operand:VF 0 "register_operand") - (minus:VF - (mult:VF - (match_operand:VF 1 "register_operand") - (match_operand:VF 2 "register_operand")) - (match_operand:VF 3 "register_operand")))] + [(set (match_operand:V_VLSF 0 "register_operand") + (minus:V_VLSF + (mult:V_VLSF + (match_operand:V_VLSF 1 "register_operand") + (match_operand:V_VLSF 2 "register_operand")) + (match_operand:V_VLSF 3 "register_operand")))] "TARGET_VECTOR && can_create_pseudo_p ()" "#" "&& 1" @@ -1219,13 +1219,13 @@ ;; ------------------------------------------------------------------------- (define_insn_and_split "fnms4" - [(set (match_operand:VF 0 "register_operand") - (minus:VF - (neg:VF - (mult:VF - (match_operand:VF 1 "register_operand") - (match_operand:VF 2 "register_operand"))) - (match_operand:VF 3 "register_operand")))] + [(set (match_operand:V_VLSF 0 "register_operand") + (minus:V_VLSF + (neg:V_VLSF + (mult:V_VLSF + (match_operand:V_VLSF 1 "register_operand") + (match_operand:V_VLSF 2 "register_operand"))) + (match_operand:V_VLSF 3 "register_operand")))] "TARGET_VECTOR && can_create_pseudo_p ()" "#" "&& 1" diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index c5a1c9061c4..f7f37da692a 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -6296,8 +6296,8 @@ ;; ------------------------------------------------------------------------------- (define_expand "@pred_mul_" - [(set (match_operand:VF 0 "register_operand") - (if_then_else:VF + [(set (match_operand:V_VLSF 0 "register_operand") + (if_then_else:V_VLSF (unspec: [(match_operand: 1 "vector_mask_operand") (match_operand 6 "vector_length_operand") @@ -6308,20 +6308,20 @@ (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM) (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE) - (plus_minus:VF - (mult:VF - (match_operand:VF 2 "register_operand") - (match_operand:VF 3 "register_operand")) - (match_operand:VF 4 "register_operand")) - (match_operand:VF 5 "vector_merge_operand")))] + (plus_minus:V_VLSF + (mult:V_VLSF + (match_operand:V_VLSF 2 "register_operand") + (match_operand:V_VLSF 3 "register_operand")) + (match_operand:V_VLSF 4 "register_operand")) + (match_operand:V_VLSF 5 "vector_merge_operand")))] "TARGET_VECTOR" { riscv_vector::prepare_ternary_operands (operands); }) (define_insn "*pred_mul__undef" - [(set (match_operand:VF 0 "register_operand" "=vd,vd,?&vd, vr, vr,?&vr") - (if_then_else:VF + [(set (match_operand:V_VLSF 0 "register_operand" "=vd,vd,?&vd, vr, vr,?&vr") + (if_then_else:V_VLSF (unspec: [(match_operand: 1 "vector_mask_operand" " vm,vm, vm,Wc1,Wc1, Wc1") (match_operand 6 "vector_length_operand" " rK,rK, rK, rK, rK, rK") @@ -6332,12 +6332,12 @@ (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM) (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE) - (plus_minus:VF - (mult:VF - (match_operand:VF 3 "register_operand" " 0,vr, vr, 0, vr, vr") - (match_operand:VF 4 "register_operand" " vr,vr, vr, vr, vr, vr")) - (match_operand:VF 5 "register_operand" " vr, 0, vr, vr, 0, vr")) - (match_operand:VF 2 "vector_undef_operand")))] + (plus_minus:V_VLSF + (mult:V_VLSF + (match_operand:V_VLSF 3 "register_operand" " 0,vr, vr, 0, vr, vr") + (match_operand:V_VLSF 4 "register_operand" " vr,vr, vr, vr, vr, vr")) + (match_operand:V_VLSF 5 "register_operand" " vr, 0, vr, vr, 0, vr")) + (match_operand:V_VLSF 2 "vector_undef_operand")))] "TARGET_VECTOR" "@ vf.vv\t%0,%4,%5%p1 @@ -6352,8 +6352,8 @@ (symbol_ref "riscv_vector::get_frm_mode (operands[10])"))]) (define_insn "*pred_" - [(set (match_operand:VF 0 "register_operand" "=vd, ?&vd, vr, ?&vr") - (if_then_else:VF + [(set (match_operand:V_VLSF 0 "register_operand" "=vd, ?&vd, vr, ?&vr") + (if_then_else:V_VLSF (unspec: [(match_operand: 1 "vector_mask_operand" " vm, vm,Wc1, Wc1") (match_operand 5 "vector_length_operand" " rK, rK, rK, rK") @@ -6364,11 +6364,11 @@ (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM) (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE) - (plus_minus:VF - (mult:VF - (match_operand:VF 2 "register_operand" " 0, vr, 0, vr") - (match_operand:VF 3 "register_operand" " vr, vr, vr, vr")) - (match_operand:VF 4 "register_operand" " vr, vr, vr, vr")) + (plus_minus:V_VLSF + (mult:V_VLSF + (match_operand:V_VLSF 2 "register_operand" " 0, vr, 0, vr") + (match_operand:V_VLSF 3 "register_operand" " vr, vr, vr, vr")) + (match_operand:V_VLSF 4 "register_operand" " vr, vr, vr, vr")) (match_dup 2)))] "TARGET_VECTOR" "@ @@ -6387,8 +6387,8 @@ (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))]) (define_insn "*pred_" - [(set (match_operand:VF 0 "register_operand" "=vd, ?&vd, vr, ?&vr") - (if_then_else:VF + [(set (match_operand:V_VLSF 0 "register_operand" "=vd, ?&vd, vr, ?&vr") + (if_then_else:V_VLSF (unspec: [(match_operand: 1 "vector_mask_operand" " vm, vm,Wc1, Wc1") (match_operand 5 "vector_length_operand" " rK, rK, rK, rK") @@ -6399,11 +6399,11 @@ (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM) (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE) - (plus_minus:VF - (mult:VF - (match_operand:VF 2 "register_operand" " vr, vr, vr, vr") - (match_operand:VF 3 "register_operand" " vr, vr, vr, vr")) - (match_operand:VF 4 "register_operand" " 0, vr, 0, vr")) + (plus_minus:V_VLSF + (mult:V_VLSF + (match_operand:V_VLSF 2 "register_operand" " vr, vr, vr, vr") + (match_operand:V_VLSF 3 "register_operand" " vr, vr, vr, vr")) + (match_operand:V_VLSF 4 "register_operand" " 0, vr, 0, vr")) (match_dup 4)))] "TARGET_VECTOR" "@ @@ -6422,8 +6422,8 @@ (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))]) (define_expand "@pred_mul__scalar" - [(set (match_operand:VF 0 "register_operand") - (if_then_else:VF + [(set (match_operand:V_VLSF 0 "register_operand") + (if_then_else:V_VLSF (unspec: [(match_operand: 1 "vector_mask_operand") (match_operand 6 "vector_length_operand") @@ -6434,19 +6434,19 @@ (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM) (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE) - (plus_minus:VF - (mult:VF - (vec_duplicate:VF + (plus_minus:V_VLSF + (mult:V_VLSF + (vec_duplicate:V_VLSF (match_operand: 2 "register_operand")) - (match_operand:VF 3 "register_operand")) - (match_operand:VF 4 "register_operand")) - (match_operand:VF 5 "register_operand")))] + (match_operand:V_VLSF 3 "register_operand")) + (match_operand:V_VLSF 4 "register_operand")) + (match_operand:V_VLSF 5 "register_operand")))] "TARGET_VECTOR" {}) (define_insn "*pred__scalar" - [(set (match_operand:VF 0 "register_operand" "=vd, ?&vd, vr, ?&vr") - (if_then_else:VF + [(set (match_operand:V_VLSF 0 "register_operand" "=vd, ?&vd, vr, ?&vr") + (if_then_else:V_VLSF (unspec: [(match_operand: 1 "vector_mask_operand" " vm, vm,Wc1, Wc1") (match_operand 5 "vector_length_operand" " rK, rK, rK, rK") @@ -6457,12 +6457,12 @@ (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM) (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE) - (plus_minus:VF - (mult:VF - (vec_duplicate:VF + (plus_minus:V_VLSF + (mult:V_VLSF + (vec_duplicate:V_VLSF (match_operand: 2 "register_operand" " f, f, f, f")) - (match_operand:VF 3 "register_operand" " 0, vr, 0, vr")) - (match_operand:VF 4 "register_operand" " vr, vr, vr, vr")) + (match_operand:V_VLSF 3 "register_operand" " 0, vr, 0, vr")) + (match_operand:V_VLSF 4 "register_operand" " vr, vr, vr, vr")) (match_dup 3)))] "TARGET_VECTOR" "@ @@ -6481,8 +6481,8 @@ (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))]) (define_insn "*pred__scalar" - [(set (match_operand:VF 0 "register_operand" "=vd, ?&vd, vr, ?&vr") - (if_then_else:VF + [(set (match_operand:V_VLSF 0 "register_operand" "=vd, ?&vd, vr, ?&vr") + (if_then_else:V_VLSF (unspec: [(match_operand: 1 "vector_mask_operand" " vm, vm,Wc1, Wc1") (match_operand 5 "vector_length_operand" " rK, rK, rK, rK") @@ -6493,12 +6493,12 @@ (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM) (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE) - (plus_minus:VF - (mult:VF - (vec_duplicate:VF + (plus_minus:V_VLSF + (mult:V_VLSF + (vec_duplicate:V_VLSF (match_operand: 2 "register_operand" " f, f, f, f")) - (match_operand:VF 3 "register_operand" " vr, vr, vr, vr")) - (match_operand:VF 4 "register_operand" " 0, vr, 0, vr")) + (match_operand:V_VLSF 3 "register_operand" " vr, vr, vr, vr")) + (match_operand:V_VLSF 4 "register_operand" " 0, vr, 0, vr")) (match_dup 4)))] "TARGET_VECTOR" "@ @@ -6517,8 +6517,8 @@ (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))]) (define_expand "@pred_mul_neg_" - [(set (match_operand:VF 0 "register_operand") - (if_then_else:VF + [(set (match_operand:V_VLSF 0 "register_operand") + (if_then_else:V_VLSF (unspec: [(match_operand: 1 "vector_mask_operand") (match_operand 6 "vector_length_operand") @@ -6529,21 +6529,21 @@ (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM) (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE) - (plus_minus:VF - (neg:VF - (mult:VF - (match_operand:VF 2 "register_operand") - (match_operand:VF 3 "register_operand"))) - (match_operand:VF 4 "register_operand")) - (match_operand:VF 5 "vector_merge_operand")))] + (plus_minus:V_VLSF + (neg:V_VLSF + (mult:V_VLSF + (match_operand:V_VLSF 2 "register_operand") + (match_operand:V_VLSF 3 "register_operand"))) + (match_operand:V_VLSF 4 "register_operand")) + (match_operand:V_VLSF 5 "vector_merge_operand")))] "TARGET_VECTOR" { riscv_vector::prepare_ternary_operands (operands); }) (define_insn "*pred_mul_neg__undef" - [(set (match_operand:VF 0 "register_operand" "=vd,vd,?&vd, vr, vr,?&vr") - (if_then_else:VF + [(set (match_operand:V_VLSF 0 "register_operand" "=vd,vd,?&vd, vr, vr,?&vr") + (if_then_else:V_VLSF (unspec: [(match_operand: 1 "vector_mask_operand" " vm,vm, vm,Wc1,Wc1, Wc1") (match_operand 6 "vector_length_operand" " rK,rK, rK, rK, rK, rK") @@ -6554,13 +6554,13 @@ (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM) (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE) - (plus_minus:VF - (neg:VF - (mult:VF - (match_operand:VF 3 "register_operand" " 0,vr, vr, 0, vr, vr") - (match_operand:VF 4 "register_operand" " vr,vr, vr, vr, vr, vr"))) - (match_operand:VF 5 "register_operand" " vr, 0, vr, vr, 0, vr")) - (match_operand:VF 2 "vector_undef_operand")))] + (plus_minus:V_VLSF + (neg:V_VLSF + (mult:V_VLSF + (match_operand:V_VLSF 3 "register_operand" " 0,vr, vr, 0, vr, vr") + (match_operand:V_VLSF 4 "register_operand" " vr,vr, vr, vr, vr, vr"))) + (match_operand:V_VLSF 5 "register_operand" " vr, 0, vr, vr, 0, vr")) + (match_operand:V_VLSF 2 "vector_undef_operand")))] "TARGET_VECTOR" "@ vf.vv\t%0,%4,%5%p1 @@ -6575,8 +6575,8 @@ (symbol_ref "riscv_vector::get_frm_mode (operands[10])"))]) (define_insn "*pred_" - [(set (match_operand:VF 0 "register_operand" "=vd, ?&vd, vr, ?&vr") - (if_then_else:VF + [(set (match_operand:V_VLSF 0 "register_operand" "=vd, ?&vd, vr, ?&vr") + (if_then_else:V_VLSF (unspec: [(match_operand: 1 "vector_mask_operand" " vm, vm,Wc1, Wc1") (match_operand 5 "vector_length_operand" " rK, rK, rK, rK") @@ -6587,12 +6587,12 @@ (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM) (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE) - (plus_minus:VF - (neg:VF - (mult:VF - (match_operand:VF 2 "register_operand" " 0, vr, 0, vr") - (match_operand:VF 3 "register_operand" " vr, vr, vr, vr"))) - (match_operand:VF 4 "register_operand" " vr, vr, vr, vr")) + (plus_minus:V_VLSF + (neg:V_VLSF + (mult:V_VLSF + (match_operand:V_VLSF 2 "register_operand" " 0, vr, 0, vr") + (match_operand:V_VLSF 3 "register_operand" " vr, vr, vr, vr"))) + (match_operand:V_VLSF 4 "register_operand" " vr, vr, vr, vr")) (match_dup 2)))] "TARGET_VECTOR" "@ @@ -6611,8 +6611,8 @@ (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))]) (define_insn "*pred_" - [(set (match_operand:VF 0 "register_operand" "=vd, ?&vd, vr, ?&vr") - (if_then_else:VF + [(set (match_operand:V_VLSF 0 "register_operand" "=vd, ?&vd, vr, ?&vr") + (if_then_else:V_VLSF (unspec: [(match_operand: 1 "vector_mask_operand" " vm, vm,Wc1, Wc1") (match_operand 5 "vector_length_operand" " rK, rK, rK, rK") @@ -6623,12 +6623,12 @@ (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM) (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE) - (plus_minus:VF - (neg:VF - (mult:VF - (match_operand:VF 2 "register_operand" " vr, vr, vr, vr") - (match_operand:VF 3 "register_operand" " vr, vr, vr, vr"))) - (match_operand:VF 4 "register_operand" " 0, vr, 0, vr")) + (plus_minus:V_VLSF + (neg:V_VLSF + (mult:V_VLSF + (match_operand:V_VLSF 2 "register_operand" " vr, vr, vr, vr") + (match_operand:V_VLSF 3 "register_operand" " vr, vr, vr, vr"))) + (match_operand:V_VLSF 4 "register_operand" " 0, vr, 0, vr")) (match_dup 4)))] "TARGET_VECTOR" "@ @@ -6647,8 +6647,8 @@ (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))]) (define_expand "@pred_mul_neg__scalar" - [(set (match_operand:VF 0 "register_operand") - (if_then_else:VF + [(set (match_operand:V_VLSF 0 "register_operand") + (if_then_else:V_VLSF (unspec: [(match_operand: 1 "vector_mask_operand") (match_operand 6 "vector_length_operand") @@ -6659,20 +6659,20 @@ (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM) (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE) - (plus_minus:VF - (neg:VF - (mult:VF - (vec_duplicate:VF + (plus_minus:V_VLSF + (neg:V_VLSF + (mult:V_VLSF + (vec_duplicate:V_VLSF (match_operand: 2 "register_operand")) - (match_operand:VF 3 "register_operand"))) - (match_operand:VF 4 "register_operand")) - (match_operand:VF 5 "register_operand")))] + (match_operand:V_VLSF 3 "register_operand"))) + (match_operand:V_VLSF 4 "register_operand")) + (match_operand:V_VLSF 5 "register_operand")))] "TARGET_VECTOR" {}) (define_insn "*pred__scalar" - [(set (match_operand:VF 0 "register_operand" "=vd, ?&vd, vr, ?&vr") - (if_then_else:VF + [(set (match_operand:V_VLSF 0 "register_operand" "=vd, ?&vd, vr, ?&vr") + (if_then_else:V_VLSF (unspec: [(match_operand: 1 "vector_mask_operand" " vm, vm,Wc1, Wc1") (match_operand 5 "vector_length_operand" " rK, rK, rK, rK") @@ -6683,13 +6683,13 @@ (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM) (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE) - (plus_minus:VF - (neg:VF - (mult:VF - (vec_duplicate:VF + (plus_minus:V_VLSF + (neg:V_VLSF + (mult:V_VLSF + (vec_duplicate:V_VLSF (match_operand: 2 "register_operand" " f, f, f, f")) - (match_operand:VF 3 "register_operand" " 0, vr, 0, vr"))) - (match_operand:VF 4 "register_operand" " vr, vr, vr, vr")) + (match_operand:V_VLSF 3 "register_operand" " 0, vr, 0, vr"))) + (match_operand:V_VLSF 4 "register_operand" " vr, vr, vr, vr")) (match_dup 3)))] "TARGET_VECTOR" "@ @@ -6708,8 +6708,8 @@ (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))]) (define_insn "*pred__scalar" - [(set (match_operand:VF 0 "register_operand" "=vd, ?&vd, vr, ?&vr") - (if_then_else:VF + [(set (match_operand:V_VLSF 0 "register_operand" "=vd, ?&vd, vr, ?&vr") + (if_then_else:V_VLSF (unspec: [(match_operand: 1 "vector_mask_operand" " vm, vm,Wc1, Wc1") (match_operand 5 "vector_length_operand" " rK, rK, rK, rK") @@ -6720,13 +6720,13 @@ (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM) (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE) - (plus_minus:VF - (neg:VF - (mult:VF - (vec_duplicate:VF + (plus_minus:V_VLSF + (neg:V_VLSF + (mult:V_VLSF + (vec_duplicate:V_VLSF (match_operand: 2 "register_operand" " f, f, f, f")) - (match_operand:VF 3 "register_operand" " vr, vr, vr, vr"))) - (match_operand:VF 4 "register_operand" " 0, vr, 0, vr")) + (match_operand:V_VLSF 3 "register_operand" " vr, vr, vr, vr"))) + (match_operand:V_VLSF 4 "register_operand" " 0, vr, 0, vr")) (match_dup 4)))] "TARGET_VECTOR" "@ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h index 7528ee73d9e..5df90704885 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h @@ -475,3 +475,12 @@ typedef double v512df __attribute__ ((vector_size (4096))); for (int i = 0; i < NUM; ++i) \ a[i] = d[i] - b[i] * c[i]; \ } + +#define DEF_FMS_VV(PREFIX, NUM, TYPE) \ + void __attribute__ ((noinline, noclone)) \ + PREFIX##_##TYPE##NUM (TYPE *restrict a, TYPE *restrict b, TYPE *restrict c, \ + TYPE *restrict d) \ + { \ + for (int i = 0; i < NUM; ++i) \ + a[i] = b[i] * c[i] - d[i]; \ + } diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fma-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fma-5.c new file mode 100644 index 00000000000..de565b76b0c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fma-5.c @@ -0,0 +1,31 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */ + +#include "def.h" + +DEF_FMA_VV (fma, 2, _Float16) +DEF_FMA_VV (fma, 4, _Float16) +DEF_FMA_VV (fma, 8, _Float16) +DEF_FMA_VV (fma, 16, _Float16) +DEF_FMA_VV (fma, 32, _Float16) +DEF_FMA_VV (fma, 64, _Float16) +DEF_FMA_VV (fma, 128, _Float16) +DEF_FMA_VV (fma, 256, _Float16) +DEF_FMA_VV (fma, 512, _Float16) +DEF_FMA_VV (fma, 1024, _Float16) +DEF_FMA_VV (fma, 2048, _Float16) + +/* { dg-final { scan-assembler-times {vfma[c-d][c-d]\.vv} 11 } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fma-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fma-6.c new file mode 100644 index 00000000000..97fd9b8cd19 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fma-6.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */ + +#include "def.h" + +DEF_FMA_VV (fma, 2, float) +DEF_FMA_VV (fma, 4, float) +DEF_FMA_VV (fma, 8, float) +DEF_FMA_VV (fma, 16, float) +DEF_FMA_VV (fma, 32, float) +DEF_FMA_VV (fma, 64, float) +DEF_FMA_VV (fma, 128, float) +DEF_FMA_VV (fma, 256, float) +DEF_FMA_VV (fma, 512, float) +DEF_FMA_VV (fma, 1024, float) + +/* { dg-final { scan-assembler-times {vfma[c-d][c-d]\.vv} 10 } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fma-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fma-7.c new file mode 100644 index 00000000000..c6dc9f7ff81 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fma-7.c @@ -0,0 +1,29 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */ + +#include "def.h" + +DEF_FMA_VV (fma, 2, double) +DEF_FMA_VV (fma, 4, double) +DEF_FMA_VV (fma, 8, double) +DEF_FMA_VV (fma, 16, double) +DEF_FMA_VV (fma, 32, double) +DEF_FMA_VV (fma, 64, double) +DEF_FMA_VV (fma, 128, double) +DEF_FMA_VV (fma, 256, double) +DEF_FMA_VV (fma, 512, double) + +/* { dg-final { scan-assembler-times {vfma[c-d][c-d]\.vv} 9 } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fms-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fms-1.c new file mode 100644 index 00000000000..491ed002563 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fms-1.c @@ -0,0 +1,31 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */ + +#include "def.h" + +DEF_FMS_VV (fms, 2, _Float16) +DEF_FMS_VV (fms, 4, _Float16) +DEF_FMS_VV (fms, 8, _Float16) +DEF_FMS_VV (fms, 16, _Float16) +DEF_FMS_VV (fms, 32, _Float16) +DEF_FMS_VV (fms, 64, _Float16) +DEF_FMS_VV (fms, 128, _Float16) +DEF_FMS_VV (fms, 256, _Float16) +DEF_FMS_VV (fms, 512, _Float16) +DEF_FMS_VV (fms, 1024, _Float16) +DEF_FMS_VV (fms, 2048, _Float16) + +/* { dg-final { scan-assembler-times {vfms[a-u][b-c]\.vv} 11 } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fms-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fms-2.c new file mode 100644 index 00000000000..ade6cb11cc5 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fms-2.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */ + +#include "def.h" + +DEF_FMS_VV (fms, 2, float) +DEF_FMS_VV (fms, 4, float) +DEF_FMS_VV (fms, 8, float) +DEF_FMS_VV (fms, 16, float) +DEF_FMS_VV (fms, 32, float) +DEF_FMS_VV (fms, 64, float) +DEF_FMS_VV (fms, 128, float) +DEF_FMS_VV (fms, 256, float) +DEF_FMS_VV (fms, 512, float) +DEF_FMS_VV (fms, 1024, float) + +/* { dg-final { scan-assembler-times {vfms[a-u][b-c]\.vv} 10 } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fms-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fms-3.c new file mode 100644 index 00000000000..1746f172ef6 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fms-3.c @@ -0,0 +1,29 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */ + +#include "def.h" + +DEF_FMS_VV (fms, 2, double) +DEF_FMS_VV (fms, 4, double) +DEF_FMS_VV (fms, 8, double) +DEF_FMS_VV (fms, 16, double) +DEF_FMS_VV (fms, 32, double) +DEF_FMS_VV (fms, 64, double) +DEF_FMS_VV (fms, 128, double) +DEF_FMS_VV (fms, 256, double) +DEF_FMS_VV (fms, 512, double) + +/* { dg-final { scan-assembler-times {vfms[a-u][b-c]\.vv} 9 } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fnma-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fnma-5.c new file mode 100644 index 00000000000..053f1eee62e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fnma-5.c @@ -0,0 +1,31 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */ + +#include "def.h" + +DEF_FNMA_VV (fnma, 2, _Float16) +DEF_FNMA_VV (fnma, 4, _Float16) +DEF_FNMA_VV (fnma, 8, _Float16) +DEF_FNMA_VV (fnma, 16, _Float16) +DEF_FNMA_VV (fnma, 32, _Float16) +DEF_FNMA_VV (fnma, 64, _Float16) +DEF_FNMA_VV (fnma, 128, _Float16) +DEF_FNMA_VV (fnma, 256, _Float16) +DEF_FNMA_VV (fnma, 512, _Float16) +DEF_FNMA_VV (fnma, 1024, _Float16) +DEF_FNMA_VV (fnma, 2048, _Float16) + +/* { dg-final { scan-assembler-times {vfnms[a-u][b-c]\.vv} 11 } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fnma-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fnma-6.c new file mode 100644 index 00000000000..9053517346c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fnma-6.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */ + +#include "def.h" + +DEF_FNMA_VV (fnma, 2, float) +DEF_FNMA_VV (fnma, 4, float) +DEF_FNMA_VV (fnma, 8, float) +DEF_FNMA_VV (fnma, 16, float) +DEF_FNMA_VV (fnma, 32, float) +DEF_FNMA_VV (fnma, 64, float) +DEF_FNMA_VV (fnma, 128, float) +DEF_FNMA_VV (fnma, 256, float) +DEF_FNMA_VV (fnma, 512, float) +DEF_FNMA_VV (fnma, 1024, float) + +/* { dg-final { scan-assembler-times {vfnms[a-u][b-c]\.vv} 10 } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fnma-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fnma-7.c new file mode 100644 index 00000000000..9952a498d93 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fnma-7.c @@ -0,0 +1,29 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */ + +#include "def.h" + +DEF_FNMA_VV (fnma, 2, double) +DEF_FNMA_VV (fnma, 4, double) +DEF_FNMA_VV (fnma, 8, double) +DEF_FNMA_VV (fnma, 16, double) +DEF_FNMA_VV (fnma, 32, double) +DEF_FNMA_VV (fnma, 64, double) +DEF_FNMA_VV (fnma, 128, double) +DEF_FNMA_VV (fnma, 256, double) +DEF_FNMA_VV (fnma, 512, double) + +/* { dg-final { scan-assembler-times {vfnms[a-u][b-c]\.vv} 9 } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */