From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 2119) id 3E6EC385C6F6; Tue, 26 Sep 2023 15:09:52 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 3E6EC385C6F6 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1695740992; bh=dH3C6mXR/Pu8nAN8Xpr3piqkkNdgO32OvFOgx/nwVj4=; h=From:To:Subject:Date:From; b=aeuk3rz+e197LK6Pov1hCvVituvEH10cJi25nFwM8j0WzOAfIMH6fb13IbvKYkiES ofETlIxNvpDgl1oclo6G3wg9jLpD09s73NeaImLKwGR1+2v57AEacte2do8qgrt2pk YgxIoqh5oPA8ZpbDR66F2YnWVyiXzxro2giIpfCo= Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Jeff Law To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/vendors/riscv/heads/gcc-13-with-riscv-opts)] RISC-V: Support VLS unary floating-point patterns X-Act-Checkin: gcc X-Git-Author: Juzhe-Zhong X-Git-Refname: refs/vendors/riscv/heads/gcc-13-with-riscv-opts X-Git-Oldrev: 42510dcebefd8920e0831c6b6c846713af39a460 X-Git-Newrev: 69d6d83c92796ddbfe0cae46a8b0a32bdc17348d Message-Id: <20230926150952.3E6EC385C6F6@sourceware.org> Date: Tue, 26 Sep 2023 15:09:52 +0000 (GMT) List-Id: https://gcc.gnu.org/g:69d6d83c92796ddbfe0cae46a8b0a32bdc17348d commit 69d6d83c92796ddbfe0cae46a8b0a32bdc17348d Author: Juzhe-Zhong Date: Tue Sep 19 19:01:24 2023 +0800 RISC-V: Support VLS unary floating-point patterns Extend current VLA patterns with VLS modes. Regression all passed. gcc/ChangeLog: * config/riscv/autovec.md: Extend VLS modes. * config/riscv/vector.md: Ditto. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/vls/def.h: Add unary test. * gcc.target/riscv/rvv/autovec/vls/neg-2.c: New test. (cherry picked from commit 5b945243c77e3ecd8dfab4b8b44f21daa3de8fe1) Diff: --- gcc/config/riscv/autovec.md | 12 ++--- gcc/config/riscv/vector.md | 20 ++++----- .../gcc.target/riscv/rvv/autovec/vls/def.h | 3 +- .../gcc.target/riscv/rvv/autovec/vls/neg-2.c | 52 ++++++++++++++++++++++ 4 files changed, 70 insertions(+), 17 deletions(-) diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md index 769ef6daa36..75ed7ae4f2e 100644 --- a/gcc/config/riscv/autovec.md +++ b/gcc/config/riscv/autovec.md @@ -1031,9 +1031,9 @@ ;; - vfneg.v/vfabs.v ;; ------------------------------------------------------------------------------- (define_insn_and_split "2" - [(set (match_operand:VF 0 "register_operand") - (any_float_unop_nofrm:VF - (match_operand:VF 1 "register_operand")))] + [(set (match_operand:V_VLSF 0 "register_operand") + (any_float_unop_nofrm:V_VLSF + (match_operand:V_VLSF 1 "register_operand")))] "TARGET_VECTOR && can_create_pseudo_p ()" "#" "&& 1" @@ -1052,9 +1052,9 @@ ;; - vfsqrt.v ;; ------------------------------------------------------------------------------- (define_insn_and_split "2" - [(set (match_operand:VF 0 "register_operand") - (any_float_unop:VF - (match_operand:VF 1 "register_operand")))] + [(set (match_operand:V_VLSF 0 "register_operand") + (any_float_unop:V_VLSF + (match_operand:V_VLSF 1 "register_operand")))] "TARGET_VECTOR && can_create_pseudo_p ()" "#" "&& 1" diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index f7f37da692a..f66ffebba24 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -6756,8 +6756,8 @@ ;; ------------------------------------------------------------------------------- (define_insn "@pred_" - [(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr") - (if_then_else:VF + [(set (match_operand:V_VLSF 0 "register_operand" "=vd, vd, vr, vr") + (if_then_else:V_VLSF (unspec: [(match_operand: 1 "vector_mask_operand" " vm, vm,Wc1,Wc1") (match_operand 4 "vector_length_operand" " rK, rK, rK, rK") @@ -6768,9 +6768,9 @@ (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM) (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE) - (any_float_unop:VF - (match_operand:VF 3 "register_operand" " vr, vr, vr, vr")) - (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))] + (any_float_unop:V_VLSF + (match_operand:V_VLSF 3 "register_operand" " vr, vr, vr, vr")) + (match_operand:V_VLSF 2 "vector_merge_operand" " vu, 0, vu, 0")))] "TARGET_VECTOR" "vf.v\t%0,%3%p1" [(set_attr "type" "") @@ -6783,8 +6783,8 @@ (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))]) (define_insn "@pred_" - [(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr") - (if_then_else:VF + [(set (match_operand:V_VLSF 0 "register_operand" "=vd, vd, vr, vr") + (if_then_else:V_VLSF (unspec: [(match_operand: 1 "vector_mask_operand" " vm, vm,Wc1,Wc1") (match_operand 4 "vector_length_operand" " rK, rK, rK, rK") @@ -6793,9 +6793,9 @@ (match_operand 7 "const_int_operand" " i, i, i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (any_float_unop_nofrm:VF - (match_operand:VF 3 "register_operand" " vr, vr, vr, vr")) - (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))] + (any_float_unop_nofrm:V_VLSF + (match_operand:V_VLSF 3 "register_operand" " vr, vr, vr, vr")) + (match_operand:V_VLSF 2 "vector_merge_operand" " vu, 0, vu, 0")))] "TARGET_VECTOR" "vf.v\t%0,%3%p1" [(set_attr "type" "") diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h index 5df90704885..d7b721b4e3e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h @@ -1,4 +1,5 @@ #include +#include typedef int8_t v1qi __attribute__ ((vector_size (1))); typedef int8_t v2qi __attribute__ ((vector_size (2))); @@ -210,7 +211,7 @@ typedef double v512df __attribute__ ((vector_size (4096))); PREFIX##_##TYPE##NUM (TYPE *restrict a, TYPE *restrict b) \ { \ for (int i = 0; i < NUM; ++i) \ - a[i] = OP b[i]; \ + a[i] = OP (b[i]); \ } #define DEF_CALL_VV(PREFIX, NUM, TYPE, CALL) \ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/neg-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/neg-2.c new file mode 100644 index 00000000000..c2ab0098afa --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/neg-2.c @@ -0,0 +1,52 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */ + +#include "def.h" + +DEF_OP_V (neg, 2, _Float16, -) +DEF_OP_V (neg, 4, _Float16, -) +DEF_OP_V (neg, 8, _Float16, -) +DEF_OP_V (neg, 16, _Float16, -) +DEF_OP_V (neg, 32, _Float16, -) +DEF_OP_V (neg, 64, _Float16, -) +DEF_OP_V (neg, 128, _Float16, -) +DEF_OP_V (neg, 256, _Float16, -) +DEF_OP_V (neg, 512, _Float16, -) +DEF_OP_V (neg, 1024, _Float16, -) +DEF_OP_V (neg, 2048, _Float16, -) + +DEF_OP_V (neg, 2, float, -) +DEF_OP_V (neg, 4, float, -) +DEF_OP_V (neg, 8, float, -) +DEF_OP_V (neg, 16, float, -) +DEF_OP_V (neg, 32, float, -) +DEF_OP_V (neg, 64, float, -) +DEF_OP_V (neg, 128, float, -) +DEF_OP_V (neg, 256, float, -) +DEF_OP_V (neg, 512, float, -) +DEF_OP_V (neg, 1024, float, -) + +DEF_OP_V (neg, 2, double, -) +DEF_OP_V (neg, 4, double, -) +DEF_OP_V (neg, 8, double, -) +DEF_OP_V (neg, 16, double, -) +DEF_OP_V (neg, 32, double, -) +DEF_OP_V (neg, 64, double, -) +DEF_OP_V (neg, 128, double, -) +DEF_OP_V (neg, 256, double, -) +DEF_OP_V (neg, 512, double, -) + +/* { dg-final { scan-assembler-times {vfneg\.v\s+v[0-9]+,\s*v[0-9]+} 30 } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */