From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 2119) id C4E0E385E000; Tue, 26 Sep 2023 15:10:27 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org C4E0E385E000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1695741027; bh=Hp0PwzHX2eIgnkypgxr8zv6d/wqLskGmUQP+rdYc2xQ=; h=From:To:Subject:Date:From; b=VdSfJJ42yBttPaYeGiK0jrwnLxXps7FJaGaWgU/Bg8252BhYNIIbCyAV36xFObjQv 9X9fxLU71UPnURwV2epHBV68AW8RdFOcPDvXZ6nkOdz+dWvf+Fa9WbjD/0iLJR1nEb judE5Tg3j6dShYRLCZJF89zqogykSF8OlIKOnXTo= Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Jeff Law To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/vendors/riscv/heads/gcc-13-with-riscv-opts)] RISC-V: Reorganize and rename combine patterns in autovec-opt.md X-Act-Checkin: gcc X-Git-Author: Lehua Ding X-Git-Refname: refs/vendors/riscv/heads/gcc-13-with-riscv-opts X-Git-Oldrev: 280909b33b8fa290c1a565740037e46fa857e17c X-Git-Newrev: 22ab5d21284a12116746f278001ea41467b1cc28 Message-Id: <20230926151027.C4E0E385E000@sourceware.org> Date: Tue, 26 Sep 2023 15:10:27 +0000 (GMT) List-Id: https://gcc.gnu.org/g:22ab5d21284a12116746f278001ea41467b1cc28 commit 22ab5d21284a12116746f278001ea41467b1cc28 Author: Lehua Ding Date: Wed Sep 20 14:48:23 2023 +0800 RISC-V: Reorganize and rename combine patterns in autovec-opt.md This patch reorganize and rename the combine patterns in autovec-opt.md by category. There shouldn't be any functional changes. The current classification includes the following categories: - Combine op + vmerge to cond_op - Combine binop + trunc to narrow_binop - Combine extend + binop to widen_binop - Combine extend + ternop to widen_ternop - Misc combine patterns gcc/ChangeLog: * config/riscv/autovec-opt.md (*not): Move and rename. (*n): Ditto. (*vtrunc): Ditto. (*trunc): Ditto. (*narrow_): Ditto. (*narrow__scalar): Ditto. (*single_widen_mult): Ditto. (*single_widen_mul): Ditto. (*single_widen_mult): Ditto. (*single_widen_mul): Ditto. (*dual_widen_fma): Ditto. (*dual_widen_fma): Ditto. (*single_widen_fma): Ditto. (*single_widen_fma): Ditto. (*dual_fma): Ditto. (*single_fma): Ditto. (*dual_fnma): Ditto. (*dual_widen_fnma): Ditto. (*single_fnma): Ditto. (*single_widen_fnma): Ditto. (*dual_fms): Ditto. (*dual_widen_fms): Ditto. (*single_fms): Ditto. (*single_widen_fms): Ditto. (*dual_fnms): Ditto. (*dual_widen_fnms): Ditto. (*single_fnms): Ditto. (*single_widen_fnms): Ditto. (cherry picked from commit 264ff8182580c57f77c6bc60381cfb2c3842b46c) Diff: --- gcc/config/riscv/autovec-opt.md | 203 ++++++++++++++++++---------------------- 1 file changed, 91 insertions(+), 112 deletions(-) diff --git a/gcc/config/riscv/autovec-opt.md b/gcc/config/riscv/autovec-opt.md index 66c77ad6ebb..a97a095691c 100644 --- a/gcc/config/riscv/autovec-opt.md +++ b/gcc/config/riscv/autovec-opt.md @@ -58,104 +58,6 @@ } ) -;; ------------------------------------------------------------------------- -;; ---- [BOOL] Binary logical operations (inverted second input) -;; ------------------------------------------------------------------------- -;; Includes: -;; - vmandnot.mm -;; - vmornot.mm -;; ------------------------------------------------------------------------- - -(define_insn_and_split "*not" - [(set (match_operand:VB_VLS 0 "register_operand" "=vr") - (bitmanip_bitwise:VB_VLS - (not:VB_VLS (match_operand:VB_VLS 2 "register_operand" " vr")) - (match_operand:VB_VLS 1 "register_operand" " vr")))] - "TARGET_VECTOR && can_create_pseudo_p ()" - "#" - "&& 1" - [(const_int 0)] - { - insn_code icode = code_for_pred_not (, mode); - riscv_vector::emit_vlmax_insn (icode, riscv_vector::BINARY_MASK_OP, operands); - DONE; - } - [(set_attr "type" "vmalu") - (set_attr "mode" "")]) - -;; ------------------------------------------------------------------------- -;; ---- [BOOL] Binary logical operations (inverted result) -;; ------------------------------------------------------------------------- -;; Includes: -;; - vmnand.mm -;; - vmnor.mm -;; - vmxnor.mm -;; ------------------------------------------------------------------------- - -(define_insn_and_split "*n" - [(set (match_operand:VB_VLS 0 "register_operand" "=vr") - (not:VB_VLS - (any_bitwise:VB_VLS - (match_operand:VB_VLS 1 "register_operand" " vr") - (match_operand:VB_VLS 2 "register_operand" " vr"))))] - "TARGET_VECTOR && can_create_pseudo_p ()" - "#" - "&& 1" - [(const_int 0)] - { - insn_code icode = code_for_pred_n (, mode); - riscv_vector::emit_vlmax_insn (icode, riscv_vector::BINARY_MASK_OP, operands); - DONE; - } - [(set_attr "type" "vmalu") - (set_attr "mode" "")]) - -;; ------------------------------------------------------------------------- -;; ---- [INT] Binary narrow shifts. -;; ------------------------------------------------------------------------- -;; Includes: -;; - vnsrl.wv/vnsrl.wx/vnsrl.wi -;; - vnsra.wv/vnsra.wx/vnsra.wi -;; ------------------------------------------------------------------------- - -(define_insn_and_split "*vtrunc" - [(set (match_operand: 0 "register_operand" "=vr,vr") - (truncate: - (any_shiftrt:VWEXTI - (match_operand:VWEXTI 1 "register_operand" " vr,vr") - (any_extend:VWEXTI - (match_operand: 2 "vector_shift_operand" " vr,vk")))))] - "TARGET_VECTOR && can_create_pseudo_p ()" - "#" - "&& 1" - [(const_int 0)] -{ - insn_code icode = code_for_pred_narrow (, mode); - riscv_vector::emit_vlmax_insn (icode, riscv_vector::BINARY_OP, operands); - DONE; -} - [(set_attr "type" "vnshift") - (set_attr "mode" "")]) - -(define_insn_and_split "*trunc" - [(set (match_operand: 0 "register_operand" "=vr") - (truncate: - (any_shiftrt:VWEXTI - (match_operand:VWEXTI 1 "register_operand" " vr") - (match_operand: 2 "csr_operand" " rK"))))] - "TARGET_VECTOR && can_create_pseudo_p ()" - "#" - "&& 1" - [(const_int 0)] -{ - operands[2] = gen_lowpart (Pmode, operands[2]); - insn_code icode = code_for_pred_narrow_scalar (, mode); - riscv_vector::emit_vlmax_insn (icode, riscv_vector::BINARY_OP, operands); - DONE; -} - [(set_attr "type" "vnshift") - (set_attr "mode" "")]) - ;; ------------------------------------------------------------------------- ;; ---- Sign-extension for vmv.x.s. ;; ------------------------------------------------------------------------- @@ -574,6 +476,48 @@ } [(set_attr "type" "vector")]) +;; ============================================================================= +;; Combine binop + trunc to narrow_binop +;; ============================================================================= + +;; Combine vsr[la].vv + trunc to vnsr[la].wv +(define_insn_and_split "*narrow_" + [(set (match_operand: 0 "register_operand" "=vr,vr") + (truncate: + (any_shiftrt:VWEXTI + (match_operand:VWEXTI 1 "register_operand" " vr,vr") + (any_extend:VWEXTI + (match_operand: 2 "vector_shift_operand" " vr,vk")))))] + "TARGET_VECTOR && can_create_pseudo_p ()" + "#" + "&& 1" + [(const_int 0)] +{ + insn_code icode = code_for_pred_narrow (, mode); + riscv_vector::emit_vlmax_insn (icode, riscv_vector::BINARY_OP, operands); + DONE; +} + [(set_attr "type" "vnshift")]) + +;; Combine vsr[la].w[xi] + trunc to vnsr[la].w[xi] +(define_insn_and_split "*narrow__scalar" + [(set (match_operand: 0 "register_operand" "=vr") + (truncate: + (any_shiftrt:VWEXTI + (match_operand:VWEXTI 1 "register_operand" " vr") + (match_operand: 2 "csr_operand" " rK"))))] + "TARGET_VECTOR && can_create_pseudo_p ()" + "#" + "&& 1" + [(const_int 0)] +{ + operands[2] = gen_lowpart (Pmode, operands[2]); + insn_code icode = code_for_pred_narrow_scalar (, mode); + riscv_vector::emit_vlmax_insn (icode, riscv_vector::BINARY_OP, operands); + DONE; +} + [(set_attr "type" "vnshift")]) + ;; ============================================================================= ;; Combine extend + binop to widen_binop ;; ============================================================================= @@ -638,7 +582,7 @@ ;; i.e. there is no vwmul.wv instruction. This is a temporary pattern ;; produced by a combine pass and if there is no further combine into ;; vwmul.vv pattern, then fall back to extend pattern and vmul.vv pattern. -(define_insn_and_split "*single_widen_mult" +(define_insn_and_split "*single_widen_mul" [(set (match_operand:VWEXTI 0 "register_operand") (mult:VWEXTI (any_extend:VWEXTI @@ -753,7 +697,7 @@ ;; i.e. there is no vfwmul.wv instruction. This is a temporary pattern ;; produced by a combine pass and if there is no further combine into ;; vfwmul.vv pattern, then fall back to extend pattern and vfmul.vv pattern. -(define_insn_and_split "*single_widen_mult" +(define_insn_and_split "*single_widen_mul" [(set (match_operand:VWEXTF 0 "register_operand") (mult:VWEXTF (float_extend:VWEXTF @@ -868,8 +812,8 @@ ;; Combine extend + ternop to widen_ternop ;; ============================================================================= -;; Combine ext + fma(vmacc,vmadd) to widen_fma (vwmacc) -(define_insn_and_split "*dual_widen_fma" +;; Combine ext + fma(vmacc,vmadd) to widen_fma (vwmacc[u]) +(define_insn_and_split "*dual_widen_fma" [(set (match_operand:VWEXTI 0 "register_operand") (plus:VWEXTI (mult:VWEXTI @@ -938,7 +882,7 @@ ;; This is a temporary pattern produced by a combine pass and if there ;; is no further combine into widen pattern, then fall back to extend ;; pattern and non-widen fma pattern. -(define_insn_and_split "*single_widen_fma" +(define_insn_and_split "*single_widen_fma" [(set (match_operand:VWEXTI 0 "register_operand") (plus:VWEXTI (mult:VWEXTI @@ -966,7 +910,7 @@ [(set_attr "type" "viwmuladd")]) ;; Combine extend + fma to widen_fma (vfwmacc) -(define_insn_and_split "*dual_fma" +(define_insn_and_split "*dual_widen_fma" [(set (match_operand:VWEXTF 0 "register_operand") (plus:VWEXTF (mult:VWEXTF @@ -991,7 +935,7 @@ ;; This is a temporary pattern produced by a combine pass and if there ;; is no further combine into widen pattern, then fall back to extend ;; pattern and non-widen fma pattern. -(define_insn_and_split "*single_fma" +(define_insn_and_split "*single_widen_fma" [(set (match_operand:VWEXTF 0 "register_operand") (plus:VWEXTF (mult:VWEXTF @@ -1018,7 +962,7 @@ [(set_attr "type" "vfwmuladd")]) ;; Combine extend + fnma to widen_fnma (vfwnmsac) -(define_insn_and_split "*dual_fnma" +(define_insn_and_split "*dual_widen_fnma" [(set (match_operand:VWEXTF 0 "register_operand") (minus:VWEXTF (match_operand:VWEXTF 1 "register_operand") @@ -1043,7 +987,7 @@ ;; This is a temporary pattern produced by a combine pass and if there ;; is no further combine into widen pattern, then fall back to extend ;; pattern and non-widen fnma pattern. -(define_insn_and_split "*single_fnma" +(define_insn_and_split "*single_widen_fnma" [(set (match_operand:VWEXTF 0 "register_operand") (minus:VWEXTF (match_operand:VWEXTF 1 "register_operand") @@ -1070,7 +1014,7 @@ [(set_attr "type" "vfwmuladd")]) ;; Combine extend + fms to widen_fms (vfwmsac) -(define_insn_and_split "*dual_fms" +(define_insn_and_split "*dual_widen_fms" [(set (match_operand:VWEXTF 0 "register_operand") (minus:VWEXTF (mult:VWEXTF @@ -1095,7 +1039,7 @@ ;; This is a temporary pattern produced by a combine pass and if there ;; is no further combine into widen pattern, then fall back to extend ;; pattern and non-widen fms pattern. -(define_insn_and_split "*single_fms" +(define_insn_and_split "*single_widen_fms" [(set (match_operand:VWEXTF 0 "register_operand") (minus:VWEXTF (mult:VWEXTF @@ -1122,7 +1066,7 @@ [(set_attr "type" "vfwmuladd")]) ;; Combine extend + fnms to widen_fnms (vfwnmacc) -(define_insn_and_split "*dual_fnms" +(define_insn_and_split "*dual_widen_fnms" [(set (match_operand:VWEXTF 0 "register_operand") (minus:VWEXTF (mult:VWEXTF @@ -1148,7 +1092,7 @@ ;; This is a temporary pattern produced by a combine pass and if there ;; is no further combine into widen pattern, then fall back to extend ;; pattern and non-widen fnms pattern. -(define_insn_and_split "*single_fnms" +(define_insn_and_split "*single_widen_fnms" [(set (match_operand:VWEXTF 0 "register_operand") (minus:VWEXTF (mult:VWEXTF @@ -1179,7 +1123,7 @@ ;; Misc combine patterns ;; ============================================================================= -;; Combine vlmax neg and UNSPEC_VCOPYSIGN +;; Combine neg + vfsgnj to vfsgnjn (define_insn_and_split "*copysign_neg" [(set (match_operand:VF 0 "register_operand") (neg:VF @@ -1197,3 +1141,38 @@ DONE; } [(set_attr "type" "vector")]) + +;; Combine vmand/vmor + vmnot to vmandnot/vmornot +(define_insn_and_split "*not" + [(set (match_operand:VB_VLS 0 "register_operand" "=vr") + (bitmanip_bitwise:VB_VLS + (not:VB_VLS (match_operand:VB_VLS 2 "register_operand" " vr")) + (match_operand:VB_VLS 1 "register_operand" " vr")))] + "TARGET_VECTOR && can_create_pseudo_p ()" + "#" + "&& 1" + [(const_int 0)] + { + insn_code icode = code_for_pred_not (, mode); + riscv_vector::emit_vlmax_insn (icode, riscv_vector::BINARY_MASK_OP, operands); + DONE; + } + [(set_attr "type" "vmalu")]) + +;; Combine vmnot + vmand/vmor/vmxor to vmnand/vmnor/vmxnor +(define_insn_and_split "*n" + [(set (match_operand:VB_VLS 0 "register_operand" "=vr") + (not:VB_VLS + (any_bitwise:VB_VLS + (match_operand:VB_VLS 1 "register_operand" " vr") + (match_operand:VB_VLS 2 "register_operand" " vr"))))] + "TARGET_VECTOR && can_create_pseudo_p ()" + "#" + "&& 1" + [(const_int 0)] + { + insn_code icode = code_for_pred_n (, mode); + riscv_vector::emit_vlmax_insn (icode, riscv_vector::BINARY_MASK_OP, operands); + DONE; + } + [(set_attr "type" "vmalu")])