From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1005) id 932E63861849; Fri, 29 Sep 2023 04:38:23 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 932E63861849 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1695962303; bh=xKdhwsZvNqZd6AiBhLf/ugt4VYhsl2WeI31hzgqcXgc=; h=From:To:Subject:Date:From; b=IcWMkiLwpcpmTXu9EzlVl0iH5FE3N6K7pzcudhiRXQ8tuQPj/xVhmgqBMSxBZygJl wLY9yWXD+xXQspwys3L6WDSZkd23AF5Q/dJ86QzMkcXjB7C6jbKO7bp0CvKsI+RhTU i4Pbe/sQY+BjOfC6BtGqrpOe0w1OESyOmcmJgHVs= Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Michael Meissner To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/users/meissner/heads/work137)] Add options to disable load and store vector pair. X-Act-Checkin: gcc X-Git-Author: Michael Meissner X-Git-Refname: refs/users/meissner/heads/work137 X-Git-Oldrev: 2fdd2ac4f5e377fead85265b6eb0f1245edaa3b3 X-Git-Newrev: 92669293016dfcec0b681ff8c6f0c903d5390c18 Message-Id: <20230929043823.932E63861849@sourceware.org> Date: Fri, 29 Sep 2023 04:38:23 +0000 (GMT) List-Id: https://gcc.gnu.org/g:92669293016dfcec0b681ff8c6f0c903d5390c18 commit 92669293016dfcec0b681ff8c6f0c903d5390c18 Author: Michael Meissner Date: Fri Sep 29 00:37:59 2023 -0400 Add options to disable load and store vector pair. 2023-09-29 Michael Meissner gcc/ * config/rs6000/mma.md (movoo): Add support for -menable-load-vector-pair and -menable-store-vector-pair. * config/rs6000/rs6000-cpus.def (OTHER_POWER10_MASKS): Likewise. (POWERPC_MASKS): Likewise. * config/rs6000/rs6000.md (rs6000_setup_reg_addr_masks): If load vector pair or store vector pair instructions are not being generated, don't allow lxvpx or stxvpx to be generated. (rs6000_option_override_internal): Add warnings if either -menable-load-vector-pair or -menable-store-vector-pair is used without having MMA instructions. (rs6000_opt_masks): Allow user to override -menable-load-vector-pair or -menable-store-vector-pair. * config/rs6000/rs6000.opt (-menable-load-vector-pair): New option. (-menable-store-vector-pair): Likewise. gcc/testsuite/ * gcc.target/powerpc/vector-pair-switch1.c: New test. * gcc.target/powerpc/vector-pair-switch2.c: New test. * gcc.target/powerpc/vector-pair-switch3.c: New test. * gcc.target/powerpc/vector-pair-switch4.c: New test. * gcc.target/powerpc/vector-pair-switch5.c: New test. Diff: --- gcc/config/rs6000/mma.md | 17 +++++--- gcc/config/rs6000/rs6000-cpus.def | 8 +++- gcc/config/rs6000/rs6000.cc | 30 +++++++++++++- gcc/config/rs6000/rs6000.opt | 8 ++++ .../gcc.target/powerpc/vector-pair-switch1.c | 16 ++++++++ .../gcc.target/powerpc/vector-pair-switch2.c | 17 ++++++++ .../gcc.target/powerpc/vector-pair-switch3.c | 17 ++++++++ .../gcc.target/powerpc/vector-pair-switch4.c | 17 ++++++++ .../gcc.target/powerpc/vector-pair-switch5.c | 47 ++++++++++++++++++++++ 9 files changed, 168 insertions(+), 9 deletions(-) diff --git a/gcc/config/rs6000/mma.md b/gcc/config/rs6000/mma.md index 575751d477e..b6cc7b28956 100644 --- a/gcc/config/rs6000/mma.md +++ b/gcc/config/rs6000/mma.md @@ -298,12 +298,19 @@ "TARGET_MMA && (gpc_reg_operand (operands[0], OOmode) || gpc_reg_operand (operands[1], OOmode))" - "@ - lxvp%X1 %x0,%1 - stxvp%X0 %x1,%0 - #" +{ + if (MEM_P (operands[0])) + return TARGET_STORE_VECTOR_PAIR ? "stxvp%X0 %x1,%0" : "#"; + + if (MEM_P (operands[1])) + return TARGET_LOAD_VECTOR_PAIR ? "lxvp%X1 %x0,%1" : "#"; + + return "#"; +} "&& reload_completed - && (!MEM_P (operands[0]) && !MEM_P (operands[1]))" + && ((MEM_P (operands[0]) && !TARGET_STORE_VECTOR_PAIR) + || (MEM_P (operands[1]) && !TARGET_LOAD_VECTOR_PAIR) + || (!MEM_P (operands[0]) && !MEM_P (operands[1])))" [(const_int 0)] { rs6000_split_multireg_move (operands[0], operands[1]); diff --git a/gcc/config/rs6000/rs6000-cpus.def b/gcc/config/rs6000/rs6000-cpus.def index 4f350da378c..8c530a22da8 100644 --- a/gcc/config/rs6000/rs6000-cpus.def +++ b/gcc/config/rs6000/rs6000-cpus.def @@ -77,10 +77,12 @@ /* Flags that need to be turned off if -mno-power10. */ /* We comment out PCREL_OPT here to disable it by default because SPEC2017 performance was degraded by it. */ -#define OTHER_POWER10_MASKS (OPTION_MASK_MMA \ +#define OTHER_POWER10_MASKS (OPTION_MASK_LOAD_VECTOR_PAIR \ + | OPTION_MASK_MMA \ | OPTION_MASK_PCREL \ /* | OPTION_MASK_PCREL_OPT */ \ - | OPTION_MASK_PREFIXED) + | OPTION_MASK_PREFIXED \ + | OPTION_MASK_STORE_VECTOR_PAIR) #define ISA_3_1_MASKS_SERVER (ISA_3_0_MASKS_SERVER \ | OPTION_MASK_POWER10 \ @@ -134,6 +136,7 @@ | OPTION_MASK_P10_FUSION \ | OPTION_MASK_HTM \ | OPTION_MASK_ISEL \ + | OPTION_MASK_LOAD_VECTOR_PAIR \ | OPTION_MASK_MFCRF \ | OPTION_MASK_MMA \ | OPTION_MASK_MODULO \ @@ -156,6 +159,7 @@ | OPTION_MASK_QUAD_MEMORY_ATOMIC \ | OPTION_MASK_RECIP_PRECISION \ | OPTION_MASK_SOFT_FLOAT \ + | OPTION_MASK_STORE_VECTOR_PAIR \ | OPTION_MASK_STRICT_ALIGN_OPTIONAL \ | OPTION_MASK_VSX) diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc index cc9253bb040..ae7d7dbd621 100644 --- a/gcc/config/rs6000/rs6000.cc +++ b/gcc/config/rs6000/rs6000.cc @@ -2711,7 +2711,9 @@ rs6000_setup_reg_addr_masks (void) /* Vector pairs can do both indexed and offset loads if the instructions are enabled, otherwise they can only do offset loads since it will be broken into two vector moves. Vector quads can - only do offset loads. */ + only do offset loads. If the user restricted generation of either + of the LXVP or STXVP instructions, do not allow indexed mode so + that we can split the load/store. */ else if ((addr_mask != 0) && TARGET_MMA && (m2 == OOmode || m2 == XOmode)) { @@ -2719,7 +2721,9 @@ rs6000_setup_reg_addr_masks (void) if (rc == RELOAD_REG_FPR || rc == RELOAD_REG_VMX) { addr_mask |= RELOAD_REG_QUAD_OFFSET; - if (m2 == OOmode) + if (m2 == OOmode + && TARGET_LOAD_VECTOR_PAIR + && TARGET_STORE_VECTOR_PAIR) addr_mask |= RELOAD_REG_INDEXED; } } @@ -4405,6 +4409,26 @@ rs6000_option_override_internal (bool global_init_p) rs6000_isa_flags &= ~OPTION_MASK_MMA; } + /* Warn if -menable-load-vector-pair or -menable-store-vector-pair are used + and MMA is not set. */ + if (!TARGET_MMA && TARGET_LOAD_VECTOR_PAIR) + { + if ((rs6000_isa_flags_explicit & OPTION_MASK_LOAD_VECTOR_PAIR) != 0) + warning (0, "%qs should not be used unless you use %qs", + "-menable-load-vector-pair", "-mmma"); + + rs6000_isa_flags &= ~OPTION_MASK_LOAD_VECTOR_PAIR; + } + + if (!TARGET_MMA && TARGET_STORE_VECTOR_PAIR) + { + if ((rs6000_isa_flags_explicit & OPTION_MASK_STORE_VECTOR_PAIR) != 0) + warning (0, "%qs should not be used unless you use %qs", + "-mstore-vector-pair", "-mmma"); + + rs6000_isa_flags &= OPTION_MASK_STORE_VECTOR_PAIR; + } + /* Enable power10 fusion if we are tuning for power10, even if we aren't generating power10 instructions. */ if (!(rs6000_isa_flags_explicit & OPTION_MASK_P10_FUSION)) @@ -24222,6 +24246,8 @@ static struct rs6000_opt_mask const rs6000_opt_masks[] = { "dlmzb", OPTION_MASK_DLMZB, false, true }, { "efficient-unaligned-vsx", OPTION_MASK_EFFICIENT_UNALIGNED_VSX, false, true }, + { "enable-load-vector-pair", OPTION_MASK_LOAD_VECTOR_PAIR, false, true }, + { "enable-store-vector-pair", OPTION_MASK_STORE_VECTOR_PAIR, false, true }, { "float128", OPTION_MASK_FLOAT128_KEYWORD, false, true }, { "float128-hardware", OPTION_MASK_FLOAT128_HW, false, true }, { "fprnd", OPTION_MASK_FPRND, false, true }, diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt index bde6d3ff664..f9061ce577f 100644 --- a/gcc/config/rs6000/rs6000.opt +++ b/gcc/config/rs6000/rs6000.opt @@ -597,6 +597,14 @@ mmma Target Mask(MMA) Var(rs6000_isa_flags) Generate (do not generate) MMA instructions. +menable-load-vector-pair +Target Undocumented Mask(LOAD_VECTOR_PAIR) Var(rs6000_isa_flags) +Generate (do not generate) load vector pair instructions. + +menable-store-vector-pair +Target Undocumented Mask(STORE_VECTOR_PAIR) Var(rs6000_isa_flags) +Generate (do not generate) store vector pair instructions. + mrelative-jumptables Target Undocumented Var(rs6000_relative_jumptables) Init(1) Save diff --git a/gcc/testsuite/gcc.target/powerpc/vector-pair-switch1.c b/gcc/testsuite/gcc.target/powerpc/vector-pair-switch1.c new file mode 100644 index 00000000000..5b575e7befa --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vector-pair-switch1.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target power10_ok } */ +/* { dg-options "-mdejagnu-cpu=power10 -O2" } */ + +/* Test if we generate load and store vector pair by default on power 10. */ + +void +test (__vector_pair *p, __vector_pair *q) +{ + *p = *q; +} + +/* { dg-final { scan-assembler-times {\mp?lxvpx?\M} 1 } } */ +/* { dg-final { scan-assembler-times {\mp?stxvpx?\M} 1 } } */ +/* { dg-final { scan-assembler-not {\mp?lxvx?\M} } } */ +/* { dg-final { scan-assembler-not {\mp?stxvx?\M} } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vector-pair-switch2.c b/gcc/testsuite/gcc.target/powerpc/vector-pair-switch2.c new file mode 100644 index 00000000000..7491d436ba6 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vector-pair-switch2.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target power10_ok } */ +/* { dg-options "-mdejagnu-cpu=power10 -O2 -mno-enable-store-vector-pair" } */ + +/* Test if we generate load vector pair but not store vector pair if + -mno-enable-store-vector-pair is used on power10. */ + +void +test (__vector_pair *p, __vector_pair *q) +{ + *p = *q; +} + +/* { dg-final { scan-assembler-times {\mp?lxvpx?\M} 1 } } */ +/* { dg-final { scan-assembler-not {\mp?stxvpx?\M} } } */ +/* { dg-final { scan-assembler-not {\mp?lxvx?\M} } } */ +/* { dg-final { scan-assembler-times {\mp?stxvx?\M} 2 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vector-pair-switch3.c b/gcc/testsuite/gcc.target/powerpc/vector-pair-switch3.c new file mode 100644 index 00000000000..f2d0251bb39 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vector-pair-switch3.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target power10_ok } */ +/* { dg-options "-mdejagnu-cpu=power10 -O2 -mno-enable-load-vector-pair" } */ + +/* Test if we do not generate load vector pair but generate store vector pair + if -mno-enable-load-vector-pair is used on power10. */ + +void +test (__vector_pair *p, __vector_pair *q) +{ + *p = *q; +} + +/* { dg-final { scan-assembler-not {\mp?lxvpx?\M} } } */ +/* { dg-final { scan-assembler-times {\mp?stxvpx?\M} 1 } } */ +/* { dg-final { scan-assembler-times {\mp?lxvx?\M} 2 } } */ +/* { dg-final { scan-assembler-not {\mp?stxvx?\M} } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vector-pair-switch4.c b/gcc/testsuite/gcc.target/powerpc/vector-pair-switch4.c new file mode 100644 index 00000000000..6bc974b67f0 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vector-pair-switch4.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target power10_ok } */ +/* { dg-options "-mdejagnu-cpu=power10 -O2 -mno-enable-load-vector-pair -mno-enable-store-vector-pair" } */ + +/* Test if we do not generate load and store vector pair if directed to on + power 10. */ + +void +test (__vector_pair *p, __vector_pair *q) +{ + *p = *q; +} + +/* { dg-final { scan-assembler-not {\mp?lxvpx?\M} } } */ +/* { dg-final { scan-assembler-not {\mp?stxvpx?\M} } } */ +/* { dg-final { scan-assembler-times {\mp?lxvx?\M} 2 } } */ +/* { dg-final { scan-assembler-times {\mp?stxvx?\M} 2 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vector-pair-switch5.c b/gcc/testsuite/gcc.target/powerpc/vector-pair-switch5.c new file mode 100644 index 00000000000..223623c8008 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vector-pair-switch5.c @@ -0,0 +1,47 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target power10_ok } */ +/* { dg-options "-mdejagnu-cpu=power10 -O2" } */ + +/* Test if we can control generating load and store vector pair via the #pragma + directive. */ + +#pragma GCC target("enable-load-vector-pair") +#pragma GCC target("enable-store-vector-pair") + +void +test_load_store (__vector_pair *p, __vector_pair *q) +{ + *p = *q; /* 1 lxvp, 1 stxvp. */ +} + +#pragma GCC target ("enable-load-vector-pair") +#pragma GCC target ("no-enable-store-vector-pair") + +void +test_load_no_store (__vector_pair *p, __vector_pair *q) +{ + *p = *q; /* 1 lxvp, 2 stxv. */ +} + +#pragma GCC target ("no-enable-load-vector-pair") +#pragma GCC target ("enable-store-vector-pair") + +void +test_store_no_load (__vector_pair *p, __vector_pair *q) +{ + *p = *q; /* 2 lxv, 1 stxvp. */ +} + +#pragma GCC target ("no-enable-load-vector-pair") +#pragma GCC target ("no-enable-store-vector-pair") + +void +test_no_load_or_store (__vector_pair *p, __vector_pair *q) +{ + *p = *q; /* 2 lxv, 2 stxv. */ +} + +/* { dg-final { scan-assembler-times {\mp?lxvpx?\M} 2 } } */ +/* { dg-final { scan-assembler-times {\mp?stxvpx?\M} 2 } } */ +/* { dg-final { scan-assembler-times {\mp?lxvx?\M} 4 } } */ +/* { dg-final { scan-assembler-times {\mp?stxvx?\M} 4 } } */