From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1005) id 38A1D3858C2C; Fri, 29 Sep 2023 04:54:35 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 38A1D3858C2C DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1695963275; bh=YFyWVatXLfXsvpfdbhxYeTPh0fJrGc1rMM3L0m3j9Gc=; h=From:To:Subject:Date:From; b=sBZvkj8iqwoKpDAimB7F/Ep4xKdCdhyNKi6UdFoorx1nRHId5eaWliSLM7cc7eMFy WXhthyzg0PN5H3Sd4r7/x/HelxjrGzTiPOq8ieL+Gra6CThqvT7LlxeOMF0Xa3IEMU +OOPhXyBuh8uX2kKzY+bmO7BKcmWESH9G8W8x/hU= Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Michael Meissner To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/users/meissner/heads/work137-dmf)] PowerPC: Add -mcpu=future. X-Act-Checkin: gcc X-Git-Author: Michael Meissner X-Git-Refname: refs/users/meissner/heads/work137-dmf X-Git-Oldrev: 146b9f331b8f24984b8b647dfcf12ef79e2be752 X-Git-Newrev: 2337221d752c8290ad3b1071b78a31c4c1d48de8 Message-Id: <20230929045435.38A1D3858C2C@sourceware.org> Date: Fri, 29 Sep 2023 04:54:35 +0000 (GMT) List-Id: https://gcc.gnu.org/g:2337221d752c8290ad3b1071b78a31c4c1d48de8 commit 2337221d752c8290ad3b1071b78a31c4c1d48de8 Author: Michael Meissner Date: Fri Sep 29 00:43:30 2023 -0400 PowerPC: Add -mcpu=future. These patches implement support for potential future PowerPC cpus. At this time, features enabled with -mcpu=future may or may not be in actual PowerPCs that will be delivered in the future. This patch adds support for the -mcpu=future and -mtune=future options. If you use -mcpu=future, the macro __ARCH_PWR_FUTURE__ is defined, and the assembler .machine directive "future" is used. Future patches in this series will add support for new instructions that may be present in future PowerPC processors. At the moment, we do not have any differences in tuning between power10 and future. It is anticipated that we may change the tuning characteristics for -mtune=future at a later time. The patches have been tested on the following platforms. I added the patches for PR target/107299 that I submitted on November 2nd before doing the builds so that GCC would build on systems using IEEE 128-bit long double. * https://gcc.gnu.org/pipermail/gcc-patches/2022-November/604834.html 2023-09-29 Michael Meissner gcc/ * config/rs6000/power10.md (power10-load): Temporarily treat -mcpu=future the same as -mcpu=power10. (power10-fused-load): Likewise. (power10-prefixed-load): Likewise. (power10-prefixed-load): Likewise. (power10-load-update): Likewise. (power10-fpload-double): Likewise. (power10-fpload-double): Likewise. (power10-prefixed-fpload-double): Likewise. (power10-prefixed-fpload-double): Likewise. (power10-fpload-update-double): Likewise. (power10-fpload-single): Likewise. (power10-fpload-update-single): Likewise. (power10-vecload): Likewise. (power10-vecload-pair): Likewise. (power10-store): Likewise. (power10-fused-store): Likewise. (power10-prefixed-store): Likewise. (power10-prefixed-store): Likewise. (power10-store-update): Likewise. (power10-vecstore-pair): Likewise. (power10-larx): Likewise. (power10-lq): Likewise. (power10-stcx): Likewise. (power10-stq): Likewise. (power10-sync): Likewise. (power10-sync): Likewise. (power10-alu): Likewise. (power10-fused_alu): Likewise. (power10-paddi): Likewise. (power10-rot): Likewise. (power10-rot-compare): Likewise. (power10-alu2): Likewise. (power10-cmp): Likewise. (power10-two): Likewise. (power10-three): Likewise. (power10-mul): Likewise. (power10-mul-compare): Likewise. (power10-div): Likewise. (power10-div-compare): Likewise. (power10-crlogical): Likewise. (power10-mfcrf): Likewise. (power10-mfcr): Likewise. (power10-mtcr): Likewise. (power10-mtjmpr): Likewise. (power10-mfjmpr): Likewise. (power10-mfjmpr): Likewise. (power10-fpsimple): Likewise. (power10-fp): Likewise. (power10-fpcompare): Likewise. (power10-sdiv): Likewise. (power10-ddiv): Likewise. (power10-sqrt): Likewise. (power10-dsqrt): Likewise. (power10-vec-2cyc): Likewise. (power10-fused-vec): Likewise. (power10-veccmp): Likewise. (power10-vecsimple): Likewise. (power10-vecnormal): Likewise. (power10-qp): Likewise. (power10-vecperm): Likewise. (power10-vecperm-compare): Likewise. (power10-prefixed-vecperm): Likewise. (power10-veccomplex): Likewise. (power10-vecfdiv): Likewise. (power10-vecdiv): Likewise. (power10-qpdiv): Likewise. (power10-qpmul): Likewise. (power10-mtvsr): Likewise. (power10-mfvsr): Likewise. (power10-mfvsr): Likewise. (power10-branch): Likewise. (power10-fused-branch): Likewise. (power10-crypto): Likewise. (power10-htm): Likewise. (power10-htm): Likewise. (power10-dfp): Likewise. (power10-dfpq): Likewise. (power10-mma): Likewise. (power10-prefixed-mma): Likewise. * config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): Define __ARCH_PWR_FUTURE__ if -mcpu=future. * config/rs6000/rs6000-cpus.def (ISA_FUTURE_MASKS): New macro. (POWERPC_MASKS): Add -mcpu=future. * config/rs6000/rs6000-opts.h (enum processor_type): Add PROCESSOR_FUTURE. * config/rs6000/rs6000-tables.opt: Regenerate. * config/rs6000/rs6000.cc (future_costs): Add -mcpu=future support. Make -mtune=future act like -mtune=power10 for now. (rs6000_option_override_internal): (rs6000_machine_from_flags): Likewise. (rs6000_reassociation_width): Likewise. (rs6000_adjust_cost): Likewise. (rs6000_issue_rate): Likewise. (rs6000_sched_reorder): Likewise. (rs6000_sched_reorder2): Likewise. (rs6000_register_move_cost): Likewise. (rs6000_opt_masks): Add -mfuture. * config/rs6000/rs6000.h (ASM_CPU_SUPPORT): Likewise. * config/rs6000/rs6000.md (cpu attribute): Add -mcpu=future support. * config/rs6000/rs6000.opt (-mfuture): New undocumented debug switch. * doc/invoke.texi (IBM RS/6000 and PowerPC Options): Document -mcpu=future. Diff: --- gcc/config/rs6000/power10.md | 142 ++++++++++++++++++------------------ gcc/config/rs6000/rs6000-c.cc | 2 + gcc/config/rs6000/rs6000-cpus.def | 6 ++ gcc/config/rs6000/rs6000-opts.h | 4 +- gcc/config/rs6000/rs6000-tables.opt | 3 + gcc/config/rs6000/rs6000.cc | 51 +++++++++++-- gcc/config/rs6000/rs6000.h | 1 + gcc/config/rs6000/rs6000.md | 2 +- gcc/config/rs6000/rs6000.opt | 4 + gcc/doc/invoke.texi | 2 +- 10 files changed, 137 insertions(+), 80 deletions(-) diff --git a/gcc/config/rs6000/power10.md b/gcc/config/rs6000/power10.md index 8e1d4e1afc6..caed2d53668 100644 --- a/gcc/config/rs6000/power10.md +++ b/gcc/config/rs6000/power10.md @@ -97,12 +97,12 @@ (eq_attr "update" "no") (eq_attr "size" "!128") (eq_attr "prefixed" "no") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,future")) "DU_any_power10,LU_power10") (define_insn_reservation "power10-fused-load" 4 (and (eq_attr "type" "fused_load_cmpi,fused_addis_load,fused_load_load") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,future")) "DU_even_power10,LU_power10") (define_insn_reservation "power10-prefixed-load" 4 @@ -110,13 +110,13 @@ (eq_attr "update" "no") (eq_attr "size" "!128") (eq_attr "prefixed" "yes") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,future")) "DU_even_power10,LU_power10") (define_insn_reservation "power10-load-update" 4 (and (eq_attr "type" "load") (eq_attr "update" "yes") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,future")) "DU_even_power10,LU_power10+SXU_power10") (define_insn_reservation "power10-fpload-double" 4 @@ -124,7 +124,7 @@ (eq_attr "update" "no") (eq_attr "size" "64") (eq_attr "prefixed" "no") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,future")) "DU_any_power10,LU_power10") (define_insn_reservation "power10-prefixed-fpload-double" 4 @@ -132,14 +132,14 @@ (eq_attr "update" "no") (eq_attr "size" "64") (eq_attr "prefixed" "yes") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,future")) "DU_even_power10,LU_power10") (define_insn_reservation "power10-fpload-update-double" 4 (and (eq_attr "type" "fpload") (eq_attr "update" "yes") (eq_attr "size" "64") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,future")) "DU_even_power10,LU_power10+SXU_power10") ; SFmode loads are cracked and have additional 3 cycles over DFmode @@ -148,27 +148,27 @@ (and (eq_attr "type" "fpload") (eq_attr "update" "no") (eq_attr "size" "32") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,future")) "DU_even_power10,LU_power10") (define_insn_reservation "power10-fpload-update-single" 7 (and (eq_attr "type" "fpload") (eq_attr "update" "yes") (eq_attr "size" "32") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,future")) "DU_even_power10,LU_power10+SXU_power10") (define_insn_reservation "power10-vecload" 4 (and (eq_attr "type" "vecload") (eq_attr "size" "!256") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,future")) "DU_any_power10,LU_power10") ; lxvp (define_insn_reservation "power10-vecload-pair" 4 (and (eq_attr "type" "vecload") (eq_attr "size" "256") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,future")) "DU_even_power10,LU_power10+SXU_power10") ; Store Unit @@ -178,12 +178,12 @@ (eq_attr "prefixed" "no") (eq_attr "size" "!128") (eq_attr "size" "!256") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,future")) "DU_any_power10,STU_power10") (define_insn_reservation "power10-fused-store" 0 (and (eq_attr "type" "fused_store_store") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,future")) "DU_even_power10,STU_power10") (define_insn_reservation "power10-prefixed-store" 0 @@ -191,52 +191,52 @@ (eq_attr "prefixed" "yes") (eq_attr "size" "!128") (eq_attr "size" "!256") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,future")) "DU_even_power10,STU_power10") ; Update forms have 2 cycle latency for updated addr reg (define_insn_reservation "power10-store-update" 2 (and (eq_attr "type" "store,fpstore") (eq_attr "update" "yes") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,future")) "DU_any_power10,STU_power10") ; stxvp (define_insn_reservation "power10-vecstore-pair" 0 (and (eq_attr "type" "vecstore") (eq_attr "size" "256") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,future")) "DU_even_power10,stu0_power10+stu1_power10") (define_insn_reservation "power10-larx" 4 (and (eq_attr "type" "load_l") (eq_attr "size" "!128") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,future")) "DU_any_power10,LU_power10") ; All load quad forms (define_insn_reservation "power10-lq" 4 (and (eq_attr "type" "load,load_l") (eq_attr "size" "128") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,future")) "DU_even_power10,LU_power10+SXU_power10") (define_insn_reservation "power10-stcx" 0 (and (eq_attr "type" "store_c") (eq_attr "size" "!128") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,future")) "DU_any_power10,STU_power10") ; All store quad forms (define_insn_reservation "power10-stq" 0 (and (eq_attr "type" "store,store_c") (eq_attr "size" "128") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,future")) "DU_even_power10,stu0_power10+stu1_power10") (define_insn_reservation "power10-sync" 1 (and (eq_attr "type" "sync,isync") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,future")) "DU_even_power10,STU_power10") @@ -248,7 +248,7 @@ (define_insn_reservation "power10-alu" 2 (and (eq_attr "type" "add,exts,integer,logical,isel") (eq_attr "prefixed" "no") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,future")) "DU_any_power10,EXU_power10") ; 4 cycle CR latency (define_bypass 4 "power10-alu" @@ -256,28 +256,28 @@ (define_insn_reservation "power10-fused_alu" 2 (and (eq_attr "type" "fused_arith_logical,fused_cmp_isel,fused_carry") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,future")) "DU_even_power10,EXU_power10") ; paddi (define_insn_reservation "power10-paddi" 2 (and (eq_attr "type" "add") (eq_attr "prefixed" "yes") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,future")) "DU_even_power10,EXU_power10") ; Rotate/shift (non-record form) (define_insn_reservation "power10-rot" 2 (and (eq_attr "type" "insert,shift") (eq_attr "dot" "no") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,future")) "DU_any_power10,EXU_power10") ; Record form rotate/shift (define_insn_reservation "power10-rot-compare" 3 (and (eq_attr "type" "insert,shift") (eq_attr "dot" "yes") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,future")) "DU_any_power10,EXU_power10") ; 5 cycle CR latency (define_bypass 5 "power10-rot-compare" @@ -285,7 +285,7 @@ (define_insn_reservation "power10-alu2" 3 (and (eq_attr "type" "cntlz,popcnt,trap") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,future")) "DU_any_power10,EXU_power10") ; 5 cycle CR latency (define_bypass 5 "power10-alu2" @@ -293,24 +293,24 @@ (define_insn_reservation "power10-cmp" 2 (and (eq_attr "type" "cmp") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,future")) "DU_any_power10,EXU_power10") ; Treat 'two' and 'three' types as 2 or 3 way cracked (define_insn_reservation "power10-two" 4 (and (eq_attr "type" "two") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,future")) "DU_even_power10,EXU_power10") (define_insn_reservation "power10-three" 6 (and (eq_attr "type" "three") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,future")) "DU_all_power10,EXU_power10") (define_insn_reservation "power10-mul" 5 (and (eq_attr "type" "mul") (eq_attr "dot" "no") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,future")) "DU_any_power10,EXU_power10") ; 4 cycle MUL->MUL latency (define_bypass 4 "power10-mul" @@ -319,7 +319,7 @@ (define_insn_reservation "power10-mul-compare" 5 (and (eq_attr "type" "mul") (eq_attr "dot" "yes") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,future")) "DU_even_power10,EXU_power10") ; 4 cycle MUL->MUL latency (define_bypass 4 "power10-mul-compare" @@ -331,13 +331,13 @@ (define_insn_reservation "power10-div" 12 (and (eq_attr "type" "div") (eq_attr "dot" "no") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,future")) "DU_any_power10,EXU_power10") (define_insn_reservation "power10-div-compare" 12 (and (eq_attr "type" "div") (eq_attr "dot" "yes") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,future")) "DU_even_power10,EXU_power10") ; 14 cycle CR latency (define_bypass 14 "power10-div-compare" @@ -345,34 +345,34 @@ (define_insn_reservation "power10-crlogical" 2 (and (eq_attr "type" "cr_logical") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,future")) "DU_any_power10,EXU_power10") (define_insn_reservation "power10-mfcrf" 2 (and (eq_attr "type" "mfcrf") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,future")) "DU_any_power10,EXU_power10") (define_insn_reservation "power10-mfcr" 3 (and (eq_attr "type" "mfcr") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,future")) "DU_even_power10,EXU_power10") ; Should differentiate between 1 cr field and > 1 since target of > 1 cr ; is cracked (define_insn_reservation "power10-mtcr" 3 (and (eq_attr "type" "mtcr") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,future")) "DU_any_power10,EXU_power10") (define_insn_reservation "power10-mtjmpr" 3 (and (eq_attr "type" "mtjmpr") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,future")) "DU_any_power10,EXU_power10") (define_insn_reservation "power10-mfjmpr" 2 (and (eq_attr "type" "mfjmpr") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,future")) "DU_any_power10,EXU_power10") @@ -380,126 +380,126 @@ (define_insn_reservation "power10-fpsimple" 3 (and (eq_attr "type" "fpsimple") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,future")) "DU_any_power10,EXU_power10") (define_insn_reservation "power10-fp" 5 (and (eq_attr "type" "fp,dmul") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,future")) "DU_any_power10,EXU_power10") (define_insn_reservation "power10-fpcompare" 3 (and (eq_attr "type" "fpcompare") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,future")) "DU_any_power10,EXU_power10") (define_insn_reservation "power10-sdiv" 22 (and (eq_attr "type" "sdiv") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,future")) "DU_any_power10,EXU_power10") (define_insn_reservation "power10-ddiv" 27 (and (eq_attr "type" "ddiv") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,future")) "DU_any_power10,EXU_power10") (define_insn_reservation "power10-sqrt" 26 (and (eq_attr "type" "ssqrt") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,future")) "DU_any_power10,EXU_power10") (define_insn_reservation "power10-dsqrt" 36 (and (eq_attr "type" "dsqrt") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,future")) "DU_any_power10,EXU_power10") (define_insn_reservation "power10-vec-2cyc" 2 (and (eq_attr "type" "vecmove,veclogical,vecexts,veccmpfx") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,future")) "DU_any_power10,EXU_power10") (define_insn_reservation "power10-fused-vec" 2 (and (eq_attr "type" "fused_vector") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,future")) "DU_even_power10,EXU_power10") (define_insn_reservation "power10-veccmp" 3 (and (eq_attr "type" "veccmp") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,future")) "DU_any_power10,EXU_power10") (define_insn_reservation "power10-vecsimple" 2 (and (eq_attr "type" "vecsimple") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,future")) "DU_any_power10,EXU_power10") (define_insn_reservation "power10-vecnormal" 5 (and (eq_attr "type" "vecfloat,vecdouble") (eq_attr "size" "!128") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,future")) "DU_any_power10,EXU_power10") (define_insn_reservation "power10-qp" 12 (and (eq_attr "type" "vecfloat,vecdouble") (eq_attr "size" "128") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,future")) "DU_any_power10,EXU_power10") (define_insn_reservation "power10-vecperm" 3 (and (eq_attr "type" "vecperm") (eq_attr "prefixed" "no") (eq_attr "dot" "no") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,future")) "DU_any_power10,EXU_power10") (define_insn_reservation "power10-vecperm-compare" 3 (and (eq_attr "type" "vecperm") (eq_attr "dot" "yes") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,future")) "DU_even_power10,EXU_power10") (define_insn_reservation "power10-prefixed-vecperm" 3 (and (eq_attr "type" "vecperm") (eq_attr "prefixed" "yes") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,future")) "DU_even_power10,EXU_power10") (define_insn_reservation "power10-veccomplex" 6 (and (eq_attr "type" "veccomplex") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,future")) "DU_any_power10,EXU_power10") (define_insn_reservation "power10-vecfdiv" 24 (and (eq_attr "type" "vecfdiv") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,future")) "DU_any_power10,EXU_power10") (define_insn_reservation "power10-vecdiv" 27 (and (eq_attr "type" "vecdiv") (eq_attr "size" "!128") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,future")) "DU_any_power10,EXU_power10") (define_insn_reservation "power10-qpdiv" 56 (and (eq_attr "type" "vecdiv") (eq_attr "size" "128") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,future")) "DU_any_power10,EXU_power10") (define_insn_reservation "power10-qpmul" 24 (and (eq_attr "type" "qmul") (eq_attr "size" "128") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,future")) "DU_any_power10,EXU_power10") (define_insn_reservation "power10-mtvsr" 2 (and (eq_attr "type" "mtvsr") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,future")) "DU_any_power10,EXU_power10") (define_insn_reservation "power10-mfvsr" 2 (and (eq_attr "type" "mfvsr") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,future")) "DU_any_power10,EXU_power10") @@ -507,26 +507,26 @@ ; Branch is 2 cycles, grouped with STU for issue (define_insn_reservation "power10-branch" 2 (and (eq_attr "type" "jmpreg,branch") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,future")) "DU_any_power10,STU_power10") (define_insn_reservation "power10-fused-branch" 3 (and (eq_attr "type" "fused_mtbc") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,future")) "DU_even_power10,STU_power10") ; Crypto (define_insn_reservation "power10-crypto" 4 (and (eq_attr "type" "crypto") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,future")) "DU_any_power10,EXU_power10") ; HTM (define_insn_reservation "power10-htm" 2 (and (eq_attr "type" "htmsimple,htm") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,future")) "DU_any_power10,EXU_power10") @@ -535,26 +535,26 @@ (define_insn_reservation "power10-dfp" 12 (and (eq_attr "type" "dfp") (eq_attr "size" "!128") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,future")) "DU_any_power10,EXU_power10") (define_insn_reservation "power10-dfpq" 12 (and (eq_attr "type" "dfp") (eq_attr "size" "128") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,future")) "DU_even_power10,EXU_power10") ; MMA (define_insn_reservation "power10-mma" 9 (and (eq_attr "type" "mma") (eq_attr "prefixed" "no") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,future")) "DU_any_power10,EXU_super_power10") (define_insn_reservation "power10-prefixed-mma" 9 (and (eq_attr "type" "mma") (eq_attr "prefixed" "yes") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,future")) "DU_even_power10,EXU_super_power10") ; 4 cycle MMA->MMA latency (define_bypass 4 "power10-mma,power10-prefixed-mma" diff --git a/gcc/config/rs6000/rs6000-c.cc b/gcc/config/rs6000/rs6000-c.cc index 65be0ac43e2..e276c20cccd 100644 --- a/gcc/config/rs6000/rs6000-c.cc +++ b/gcc/config/rs6000/rs6000-c.cc @@ -447,6 +447,8 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT flags) rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR9"); if ((flags & OPTION_MASK_POWER10) != 0) rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR10"); + if ((flags & OPTION_MASK_FUTURE) != 0) + rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR_FUTURE"); if ((flags & OPTION_MASK_SOFT_FLOAT) != 0) rs6000_define_or_undefine_macro (define_p, "_SOFT_FLOAT"); if ((flags & OPTION_MASK_RECIP_PRECISION) != 0) diff --git a/gcc/config/rs6000/rs6000-cpus.def b/gcc/config/rs6000/rs6000-cpus.def index 8c530a22da8..a6d9d7bf9a8 100644 --- a/gcc/config/rs6000/rs6000-cpus.def +++ b/gcc/config/rs6000/rs6000-cpus.def @@ -88,6 +88,10 @@ | OPTION_MASK_POWER10 \ | OTHER_POWER10_MASKS) +/* Flags for a potential future processor that may or may not be delivered. */ +#define ISA_FUTURE_MASKS (ISA_3_1_MASKS_SERVER \ + | OPTION_MASK_FUTURE) + /* Flags that need to be turned off if -mno-power9-vector. */ #define OTHER_P9_VECTOR_MASKS (OPTION_MASK_FLOAT128_HW \ | OPTION_MASK_P9_MINMAX) @@ -134,6 +138,7 @@ | OPTION_MASK_FPRND \ | OPTION_MASK_POWER10 \ | OPTION_MASK_P10_FUSION \ + | OPTION_MASK_FUTURE \ | OPTION_MASK_HTM \ | OPTION_MASK_ISEL \ | OPTION_MASK_LOAD_VECTOR_PAIR \ @@ -267,3 +272,4 @@ RS6000_CPU ("powerpc64", PROCESSOR_POWERPC64, OPTION_MASK_PPC_GFXOPT RS6000_CPU ("powerpc64le", PROCESSOR_POWER8, MASK_POWERPC64 | ISA_2_7_MASKS_SERVER | OPTION_MASK_HTM) RS6000_CPU ("rs64", PROCESSOR_RS64A, OPTION_MASK_PPC_GFXOPT | MASK_POWERPC64) +RS6000_CPU ("future", PROCESSOR_FUTURE, MASK_POWERPC64 | ISA_FUTURE_MASKS) diff --git a/gcc/config/rs6000/rs6000-opts.h b/gcc/config/rs6000/rs6000-opts.h index 8040cfdc06e..f56f01d6fa5 100644 --- a/gcc/config/rs6000/rs6000-opts.h +++ b/gcc/config/rs6000/rs6000-opts.h @@ -67,7 +67,9 @@ enum processor_type PROCESSOR_MPCCORE, PROCESSOR_CELL, PROCESSOR_PPCA2, - PROCESSOR_TITAN + PROCESSOR_TITAN, + + PROCESSOR_FUTURE }; diff --git a/gcc/config/rs6000/rs6000-tables.opt b/gcc/config/rs6000/rs6000-tables.opt index b82f8205fa1..3ff28e39f6c 100644 --- a/gcc/config/rs6000/rs6000-tables.opt +++ b/gcc/config/rs6000/rs6000-tables.opt @@ -197,3 +197,6 @@ Enum(rs6000_cpu_opt_value) String(powerpc64le) Value(55) EnumValue Enum(rs6000_cpu_opt_value) String(rs64) Value(56) +EnumValue +Enum(rs6000_cpu_opt_value) String(future) Value(57) + diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc index ae7d7dbd621..3c97fe814aa 100644 --- a/gcc/config/rs6000/rs6000.cc +++ b/gcc/config/rs6000/rs6000.cc @@ -1085,6 +1085,27 @@ struct processor_costs power10_cost = { COSTS_N_INSNS (2), /* SF->DF convert */ }; +/* Instruction costs on Future processors. At the moment, this is a copy of + the power10 costs, but it is expected to change over time.. */ +static const +struct processor_costs future_cost = { + COSTS_N_INSNS (2), /* mulsi */ + COSTS_N_INSNS (2), /* mulsi_const */ + COSTS_N_INSNS (2), /* mulsi_const9 */ + COSTS_N_INSNS (2), /* muldi */ + COSTS_N_INSNS (6), /* divsi */ + COSTS_N_INSNS (6), /* divdi */ + COSTS_N_INSNS (2), /* fp */ + COSTS_N_INSNS (2), /* dmul */ + COSTS_N_INSNS (11), /* sdiv */ + COSTS_N_INSNS (13), /* ddiv */ + 128, /* cache line size */ + 32, /* l1 cache */ + 512, /* l2 cache */ + 16, /* prefetch streams */ + COSTS_N_INSNS (2), /* SF->DF convert */ +}; + /* Instruction costs on POWER A2 processors. */ static const struct processor_costs ppca2_cost = { @@ -4462,6 +4483,7 @@ rs6000_option_override_internal (bool global_init_p) && rs6000_tune != PROCESSOR_POWER8 && rs6000_tune != PROCESSOR_POWER9 && rs6000_tune != PROCESSOR_POWER10 + && rs6000_tune != PROCESSOR_FUTURE && rs6000_tune != PROCESSOR_PPCA2 && rs6000_tune != PROCESSOR_CELL && rs6000_tune != PROCESSOR_PPC476); @@ -4476,6 +4498,7 @@ rs6000_option_override_internal (bool global_init_p) || rs6000_tune == PROCESSOR_POWER8 || rs6000_tune == PROCESSOR_POWER9 || rs6000_tune == PROCESSOR_POWER10 + || rs6000_tune == PROCESSOR_FUTURE || rs6000_tune == PROCESSOR_PPCE500MC || rs6000_tune == PROCESSOR_PPCE500MC64 || rs6000_tune == PROCESSOR_PPCE5500 @@ -4778,6 +4801,10 @@ rs6000_option_override_internal (bool global_init_p) rs6000_cost = &power10_cost; break; + case PROCESSOR_FUTURE: + rs6000_cost = &future_cost; + break; + case PROCESSOR_PPCA2: rs6000_cost = &ppca2_cost; break; @@ -5934,6 +5961,8 @@ rs6000_machine_from_flags (void) /* Disable the flags that should never influence the .machine selection. */ flags &= ~(OPTION_MASK_PPC_GFXOPT | OPTION_MASK_PPC_GPOPT | OPTION_MASK_ISEL); + if ((flags & (ISA_FUTURE_MASKS & ~ISA_3_1_MASKS_SERVER)) != 0) + return "future"; if ((flags & (ISA_3_1_MASKS_SERVER & ~ISA_3_0_MASKS_SERVER)) != 0) return "power10"; if ((flags & (ISA_3_0_MASKS_SERVER & ~ISA_2_7_MASKS_SERVER)) != 0) @@ -10192,6 +10221,7 @@ rs6000_reassociation_width (unsigned int opc ATTRIBUTE_UNUSED, case PROCESSOR_POWER8: case PROCESSOR_POWER9: case PROCESSOR_POWER10: + case PROCESSOR_FUTURE: if (DECIMAL_FLOAT_MODE_P (mode)) return 1; if (VECTOR_MODE_P (mode)) @@ -18022,7 +18052,8 @@ rs6000_adjust_cost (rtx_insn *insn, int dep_type, rtx_insn *dep_insn, int cost, /* Separate a load from a narrower, dependent store. */ if ((rs6000_sched_groups || rs6000_tune == PROCESSOR_POWER9 - || rs6000_tune == PROCESSOR_POWER10) + || rs6000_tune == PROCESSOR_POWER10 + || rs6000_tune == PROCESSOR_FUTURE) && GET_CODE (PATTERN (insn)) == SET && GET_CODE (PATTERN (dep_insn)) == SET && MEM_P (XEXP (PATTERN (insn), 1)) @@ -18061,6 +18092,7 @@ rs6000_adjust_cost (rtx_insn *insn, int dep_type, rtx_insn *dep_insn, int cost, || rs6000_tune == PROCESSOR_POWER8 || rs6000_tune == PROCESSOR_POWER9 || rs6000_tune == PROCESSOR_POWER10 + || rs6000_tune == PROCESSOR_FUTURE || rs6000_tune == PROCESSOR_CELL) && recog_memoized (dep_insn) && (INSN_CODE (dep_insn) >= 0)) @@ -18635,6 +18667,7 @@ rs6000_issue_rate (void) case PROCESSOR_POWER9: return 6; case PROCESSOR_POWER10: + case PROCESSOR_FUTURE: return 8; default: return 1; @@ -19350,8 +19383,10 @@ rs6000_sched_reorder (FILE *dump ATTRIBUTE_UNUSED, int sched_verbose, if (rs6000_tune == PROCESSOR_POWER6) load_store_pendulum = 0; - /* Do Power10 dependent reordering. */ - if (rs6000_tune == PROCESSOR_POWER10 && last_scheduled_insn) + /* Do Power10 dependent reordering. For now, assume "future" has the same + dependent reordering as power10. */ + if ((rs6000_tune == PROCESSOR_POWER10 + || rs6000_tune == PROCESSOR_FUTURE) && last_scheduled_insn) power10_sched_reorder (ready, n_ready - 1); return rs6000_issue_rate (); @@ -19375,8 +19410,10 @@ rs6000_sched_reorder2 (FILE *dump, int sched_verbose, rtx_insn **ready, && recog_memoized (last_scheduled_insn) >= 0) return power9_sched_reorder2 (ready, *pn_ready - 1); - /* Do Power10 dependent reordering. */ - if (rs6000_tune == PROCESSOR_POWER10 && last_scheduled_insn) + /* Do Power10 dependent reordering. For now, assume "future" has the same + dependent reordering as power10. */ + if ((rs6000_tune == PROCESSOR_POWER10 + || rs6000_tune == PROCESSOR_FUTURE) && last_scheduled_insn) return power10_sched_reorder (ready, *pn_ready - 1); return cached_can_issue_more; @@ -22592,7 +22629,8 @@ rs6000_register_move_cost (machine_mode mode, allocation a move within the same class might turn out to be a nop. */ if (rs6000_tune == PROCESSOR_POWER9 - || rs6000_tune == PROCESSOR_POWER10) + || rs6000_tune == PROCESSOR_POWER10 + || rs6000_tune == PROCESSOR_FUTURE) ret = 3 * hard_regno_nregs (FIRST_GPR_REGNO, mode); else ret = 4 * hard_regno_nregs (FIRST_GPR_REGNO, mode); @@ -24252,6 +24290,7 @@ static struct rs6000_opt_mask const rs6000_opt_masks[] = { "float128-hardware", OPTION_MASK_FLOAT128_HW, false, true }, { "fprnd", OPTION_MASK_FPRND, false, true }, { "power10", OPTION_MASK_POWER10, false, true }, + { "future", OPTION_MASK_FUTURE, false, true }, { "hard-dfp", OPTION_MASK_DFP, false, true }, { "htm", OPTION_MASK_HTM, false, true }, { "isel", OPTION_MASK_ISEL, false, true }, diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h index 22595f6ebd7..a9c9a11765c 100644 --- a/gcc/config/rs6000/rs6000.h +++ b/gcc/config/rs6000/rs6000.h @@ -163,6 +163,7 @@ mcpu=e5500: -me5500; \ mcpu=e6500: -me6500; \ mcpu=titan: -mtitan; \ + mcpu=future: -mfuture; \ !mcpu*: %{mpower9-vector: -mpower9; \ mpower8-vector|mcrypto|mdirect-move|mhtm: -mpower8; \ mvsx: -mpower7; \ diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 1b6b6cb5bbe..bcb96b59f79 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -351,7 +351,7 @@ ppc403,ppc405,ppc440,ppc476, ppc8540,ppc8548,ppce300c2,ppce300c3,ppce500mc,ppce500mc64,ppce5500,ppce6500, power4,power5,power6,power7,power8,power9,power10, - rs64a,mpccore,cell,ppca2,titan" + rs64a,mpccore,cell,ppca2,titan,future" (const (symbol_ref "(enum attr_cpu) rs6000_tune"))) ;; The ISA we implement. diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt index f9061ce577f..42d4e9e1cb8 100644 --- a/gcc/config/rs6000/rs6000.opt +++ b/gcc/config/rs6000/rs6000.opt @@ -628,6 +628,10 @@ mieee128-constant Target Var(TARGET_IEEE128_CONSTANT) Init(1) Save Generate (do not generate) code that uses the LXVKQ instruction. +mfuture +Target Undocumented Mask(FUTURE) Var(rs6000_isa_flags) +Generate (do not generate) future instructions. + ; Documented parameters -param=rs6000-vect-unroll-limit= diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 4085fc90907..158314d8860 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -29742,7 +29742,7 @@ Supported values for @var{cpu_type} are @samp{401}, @samp{403}, @samp{titan}, @samp{power3}, @samp{power4}, @samp{power5}, @samp{power5+}, @samp{power6}, @samp{power6x}, @samp{power7}, @samp{power8}, @samp{power9}, @samp{power10}, @samp{powerpc}, @samp{powerpc64}, -@samp{powerpc64le}, @samp{rs64}, and @samp{native}. +@samp{powerpc64le}, @samp{rs64}, @samp{future}, and @samp{native}. @option{-mcpu=powerpc}, @option{-mcpu=powerpc64}, and @option{-mcpu=powerpc64le} specify pure 32-bit PowerPC (either