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From: Michael Meissner <meissner@gcc.gnu.org> To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/users/meissner/heads/work137-vsize)] Add -mvector-size-32 tests. Date: Fri, 29 Sep 2023 05:33:57 +0000 (GMT) [thread overview] Message-ID: <20230929053357.D9A883858C52@sourceware.org> (raw) https://gcc.gnu.org/g:c44a2caf9d49f86635c6ce1a3477050f112f9ba3 commit c44a2caf9d49f86635c6ce1a3477050f112f9ba3 Author: Michael Meissner <meissner@linux.ibm.com> Date: Fri Sep 29 01:33:39 2023 -0400 Add -mvector-size-32 tests. 2023-09-28 Michael Meissner <meissner@linux.ibm.com> gcc/testsuite/ * gcc.target/powerpc/vector-size-32-1.c: New test. * gcc.target/powerpc/vector-size-32-2.c: New test. * gcc.target/powerpc/vector-size-32-3.c: New test. * gcc.target/powerpc/vector-size-32-4.c: New test. * gcc.target/powerpc/vector-size-32-5.c: New test. * gcc.target/powerpc/vector-size-32-6.c: New test. Diff: --- gcc/config/rs6000/vector-pair.md | 540 +++++++++++++++++++++ .../gcc.target/powerpc/vector-size-32-1.c | 85 ++++ .../gcc.target/powerpc/vector-size-32-2.c | 96 ++++ .../gcc.target/powerpc/vector-size-32-3.c | 137 ++++++ .../gcc.target/powerpc/vector-size-32-4.c | 137 ++++++ .../gcc.target/powerpc/vector-size-32-5.c | 137 ++++++ .../gcc.target/powerpc/vector-size-32-6.c | 137 ++++++ 7 files changed, 1269 insertions(+) diff --git a/gcc/config/rs6000/vector-pair.md b/gcc/config/rs6000/vector-pair.md new file mode 100644 index 00000000000..61c45fb1d5f --- /dev/null +++ b/gcc/config/rs6000/vector-pair.md @@ -0,0 +1,540 @@ +;; Vector pair arithmetic and logical instruction support. +;; Copyright (C) 2020-2023 Free Software Foundation, Inc. +;; Contributed by Peter Bergner <bergner@linux.ibm.com> and +;; Michael Meissner <meissner@linux.ibm.com> +;; +;; This file is part of GCC. +;; +;; GCC is free software; you can redistribute it and/or modify it +;; under the terms of the GNU General Public License as published +;; by the Free Software Foundation; either version 3, or (at your +;; option) any later version. +;; +;; GCC is distributed in the hope that it will be useful, but WITHOUT +;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY +;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public +;; License for more details. +;; +;; You should have received a copy of the GNU General Public License +;; along with GCC; see the file COPYING3. If not see +;; <http://www.gnu.org/licenses/>. + +;; This function adds support for doing vector operations on pairs of vector +;; registers. Most of the instructions use vector pair instructions to load +;; and possibly store registers, but splitting the operation after register +;; allocation to do 2 separate operations. The second scheduler pass can +;; interleave other instructions between these pairs of instructions if +;; possible. + +;; Iterator for all vector pair modes +(define_mode_iterator VPAIR [V32QI V16HI V8SI V4DI V8SF V4DF]) + +;; Iterator for the integer vector pair modes +(define_mode_iterator VPAIR_INT [V32QI V16HI V8SI V4DI]) + +;; Special iterators for NEG (V4SI and V2DI have vneg{w,d}), while V16QI and +;; V8HI have to use a subtract from 0. +(define_mode_iterator VPAIR_NEG_VNEG [V4DI V8SI]) +(define_mode_iterator VPAIR_NEG_SUB [V32QI V16HI]) + +;; Iterator for the floating point vector pair modes +(define_mode_iterator VPAIR_FP [V8SF V4DF]) + +;; Iterator doing unary/binary arithmetic on vector pairs. Split it into +;; integer and floating point operations. +(define_code_iterator VPAIR_INT_UNARY [not]) +(define_code_iterator VPAIR_INT_BINARY [plus minus smin smax]) +(define_code_iterator VPAIR_INT_LOGICAL [and ior xor]) + +(define_code_iterator VPAIR_FP_UNARY [abs neg]) +(define_code_iterator VPAIR_FP_BINARY [plus minus mult smin smax]) + +;; Give the insn name from the opertion +(define_code_attr vpair_op [(abs "abs") + (and "and") + (fma "fma") + (ior "ior") + (minus "sub") + (mult "mul") + (not "one_cmpl") + (neg "neg") + (plus "add") + (smin "smin") + (smax "smax") + (umin "umin") + (umax "umax") + (xor "xor")]) + +;; Vector pair move support. +(define_expand "mov<mode>" + [(set (match_operand:VPAIR 0 "nonimmediate_operand") + (match_operand:VPAIR 1 "input_operand"))] + "TARGET_MMA && TARGET_VECTOR_SIZE_32" +{ + rs6000_emit_move (operands[0], operands[1], <MODE>mode); + DONE; +}) + +(define_insn_and_split "*mov<mode>" + [(set (match_operand:VPAIR 0 "nonimmediate_operand" "=wa,m,wa,wa,wa") + (match_operand:VPAIR 1 "input_operand" "m,wa,wa,j,eP"))] + "TARGET_MMA && TARGET_VECTOR_SIZE_32 + && (gpc_reg_operand (operands[0], <MODE>mode) + || gpc_reg_operand (operands[1], <MODE>mode))" +{ + if (MEM_P (operands[0])) + return TARGET_STORE_VECTOR_PAIR ? "stxvp%X0 %x1,%0" : "#"; + + if (MEM_P (operands[1])) + return TARGET_LOAD_VECTOR_PAIR ? "lxvp%X1 %x0,%1" : "#"; + + return "#"; +} + "&& reload_completed + && ((MEM_P (operands[0]) && !TARGET_STORE_VECTOR_PAIR) + || (MEM_P (operands[1]) && !TARGET_LOAD_VECTOR_PAIR) + || (!MEM_P (operands[0]) && !MEM_P (operands[1])))" + [(const_int 0)] +{ + rs6000_split_multireg_move (operands[0], operands[1]); + DONE; +} + [(set_attr "type" "vecload,vecstore,veclogical,vecperm,vecperm") + (set_attr "size" "256") + (set_attr "length" "*,*,8,8,40")]) + +\f +;; Vector pair floating point arithmetic unary operations +(define_insn_and_split "<vpair_op><mode>2" + [(set (match_operand:VPAIR_FP 0 "vsx_register_operand" "=wa") + (VPAIR_FP_UNARY:VPAIR_FP + (match_operand:VPAIR_FP 1 "vsx_register_operand" "wa")))] + "TARGET_MMA && TARGET_VECTOR_SIZE_32" + "#" + "&& reload_completed" + [(const_int 0)] +{ + split_unary_vector_pair (<VPAIR_VECTOR>mode, operands, + gen_<vpair_op><vpair_vector>2); + DONE; +} + [(set_attr "length" "8")]) + +;; Optimize negative absolute value (both floating point and integer) +(define_insn_and_split "nabs<mode>2" + [(set (match_operand:VPAIR_FP 0 "vsx_register_operand" "=wa") + (neg:VPAIR_FP + (abs:VPAIR_FP + (match_operand:VPAIR_FP 1 "vsx_register_operand" "wa"))))] + "TARGET_MMA && TARGET_VECTOR_SIZE_32" + "#" + "&& reload_completed" + [(const_int 0)] +{ + split_unary_vector_pair (<VPAIR_VECTOR>mode, operands, + gen_vsx_nabs<vpair_vector>2); + DONE; +} + [(set_attr "length" "8")]) + +;; Vector pair floating point arithmetic binary operations +(define_insn_and_split "<vpair_op><mode>3" + [(set (match_operand:VPAIR_FP 0 "vsx_register_operand" "=wa") + (VPAIR_FP_BINARY:VPAIR_FP + (match_operand:VPAIR_FP 1 "vsx_register_operand" "wa") + (match_operand:VPAIR_FP 2 "vsx_register_operand" "wa")))] + "TARGET_MMA && TARGET_VECTOR_SIZE_32" + "#" + "&& reload_completed" + [(const_int 0)] +{ + split_binary_vector_pair (<VPAIR_VECTOR>mode, operands, + gen_<vpair_op><vpair_vector>3); + DONE; +} + [(set_attr "length" "8")]) + +;; Vector pair floating point fused multiply-add +(define_insn_and_split "fma<mode>3" + [(set (match_operand:VPAIR_FP 0 "vsx_register_operand" "=wa,wa") + (fma:VPAIR_FP + (match_operand:VPAIR_FP 1 "vsx_register_operand" "%wa,wa") + (match_operand:VPAIR_FP 2 "vsx_register_operand" "wa,0") + (match_operand:VPAIR_FP 3 "vsx_register_operand" "0,wa")))] + "TARGET_MMA && TARGET_VECTOR_SIZE_32" + "#" + "&& reload_completed" + [(const_int 0)] +{ + split_fma_vector_pair (<VPAIR_VECTOR>mode, operands, + gen_fma<vpair_vector>4); + DONE; +} + [(set_attr "length" "8")]) + +;; Vector pair floating point fused multiply-subtract +(define_insn_and_split "fms<mode>3" + [(set (match_operand:VPAIR_FP 0 "vsx_register_operand" "=wa,wa") + (fma:VPAIR_FP + (match_operand:VPAIR_FP 1 "vsx_register_operand" "%wa,wa") + (match_operand:VPAIR_FP 2 "vsx_register_operand" "wa,0") + (neg:VPAIR_FP + (match_operand:VPAIR_FP 3 "vsx_register_operand" "0,wa"))))] + "TARGET_MMA && TARGET_VECTOR_SIZE_32" + "#" + "&& reload_completed" + [(const_int 0)] +{ + split_fma_vector_pair (<VPAIR_VECTOR>mode, operands, + gen_fms<vpair_vector>4); + DONE; +} + [(set_attr "length" "8")]) + +;; Vector pair floating point negative fused multiply-add +(define_insn_and_split "nfma<mode>3" + [(set (match_operand:VPAIR_FP 0 "vsx_register_operand" "=wa,wa") + (neg:VPAIR_FP + (fma:VPAIR_FP + (match_operand:VPAIR_FP 1 "vsx_register_operand" "%wa,wa") + (match_operand:VPAIR_FP 2 "vsx_register_operand" "wa,0") + (match_operand:VPAIR_FP 3 "vsx_register_operand" "0,wa"))))] + "TARGET_MMA && TARGET_VECTOR_SIZE_32" + "#" + "&& reload_completed" + [(const_int 0)] +{ + split_fma_vector_pair (<VPAIR_VECTOR>mode, operands, + gen_nfma<vpair_vector>4); + DONE; +} + [(set_attr "length" "8")]) + +;; Vector pair floating point fused negative multiply-subtract +(define_insn_and_split "nfms<mode>3" + [(set (match_operand:VPAIR_FP 0 "vsx_register_operand" "=wa,wa") + (neg:VPAIR_FP + (fma:VPAIR_FP + (match_operand:VPAIR_FP 1 "vsx_register_operand" "%wa,wa") + (match_operand:VPAIR_FP 2 "vsx_register_operand" "wa,0") + (neg:VPAIR_FP + (match_operand:VPAIR_FP 3 "vsx_register_operand" "0,wa")))))] + "TARGET_MMA && TARGET_VECTOR_SIZE_32" + "#" + "&& reload_completed" + [(const_int 0)] +{ + split_fma_vector_pair (<VPAIR_VECTOR>mode, operands, + gen_nfms<vpair_vector>4); + DONE; +} + [(set_attr "length" "8")]) + +;; Optimize vector pair (a * b) + c into fma (a, b, c) +(define_insn_and_split "*fma_fpcontract_<mode>3" + [(set (match_operand:VPAIR_FP 0 "vsx_register_operand" "=wa,wa") + (plus:VPAIR_FP + (mult:VPAIR_FP + (match_operand:VPAIR_FP 1 "vsx_register_operand" "%wa,wa") + (match_operand:VPAIR_FP 2 "vsx_register_operand" "wa,0")) + (match_operand:VPAIR_FP 3 "vsx_register_operand" "0,wa")))] + "TARGET_MMA && TARGET_VECTOR_SIZE_32 + && flag_fp_contract_mode == FP_CONTRACT_FAST" + "#" + "&& 1" + [(set (match_dup 0) + (fma:VPAIR_FP (match_dup 1) + (match_dup 2) + (match_dup 3)))] +{ +} + [(set_attr "length" "8")]) + +;; Optimize vector pair (a * b) - c into fma (a, b, -c) +(define_insn_and_split "*fms_fpcontract_<mode>3" + [(set (match_operand:VPAIR_FP 0 "vsx_register_operand" "=wa,wa") + (minus:VPAIR_FP + (mult:VPAIR_FP + (match_operand:VPAIR_FP 1 "vsx_register_operand" "%wa,wa") + (match_operand:VPAIR_FP 2 "vsx_register_operand" "wa,0")) + (match_operand:VPAIR_FP 3 "vsx_register_operand" "0,wa")))] + "TARGET_MMA && TARGET_VECTOR_SIZE_32 + && flag_fp_contract_mode == FP_CONTRACT_FAST" + "#" + "&& 1" + [(set (match_dup 0) + (fma:VPAIR_FP (match_dup 1) + (match_dup 2) + (neg:VPAIR_FP + (match_dup 3))))] +{ +} + [(set_attr "length" "8")]) + +;; Optimize vector pair -((a * b) + c) into -fma (a, b, c) +(define_insn_and_split "*nfma_fpcontract_<mode>3" + [(set (match_operand:VPAIR_FP 0 "vsx_register_operand" "=wa,wa") + (neg:VPAIR_FP + (plus:VPAIR_FP + (mult:VPAIR_FP + (match_operand:VPAIR_FP 1 "vsx_register_operand" "%wa,wa") + (match_operand:VPAIR_FP 2 "vsx_register_operand" "wa,0")) + (match_operand:VPAIR_FP 3 "vsx_register_operand" "0,wa"))))] + "TARGET_MMA && TARGET_VECTOR_SIZE_32 + && flag_fp_contract_mode == FP_CONTRACT_FAST" + "#" + "&& 1" + [(set (match_dup 0) + (neg:VPAIR_FP + (fma:VPAIR_FP (match_dup 1) + (match_dup 2) + (match_dup 3))))] +{ +} + [(set_attr "length" "8")]) + +;; Optimize vector pair -((a * b) - c) into -fma (a, b, -c) +(define_insn_and_split "*nfms_fpcontract_<mode>3" + [(set (match_operand:VPAIR_FP 0 "vsx_register_operand" "=wa,wa") + (neg:VPAIR_FP + (minus:VPAIR_FP + (mult:VPAIR_FP + (match_operand:VPAIR_FP 1 "vsx_register_operand" "%wa,wa") + (match_operand:VPAIR_FP 2 "vsx_register_operand" "wa,0")) + (match_operand:VPAIR_FP 3 "vsx_register_operand" "0,wa"))))] + "TARGET_MMA && TARGET_VECTOR_SIZE_32 + && flag_fp_contract_mode == FP_CONTRACT_FAST" + "#" + "&& 1" + [(set (match_dup 0) + (neg:VPAIR_FP + (fma:VPAIR_FP (match_dup 1) + (match_dup 2) + (neg:VPAIR_FP + (match_dup 3)))))] +{ +} + [(set_attr "length" "8")]) + +\f +;; Vector pair integer arithmetic unary operations +(define_insn_and_split "<vpair_op><mode>2" + [(set (match_operand:VPAIR_INT 0 "vsx_register_operand" "=wa") + (VPAIR_INT_UNARY:VPAIR_INT + (match_operand:VPAIR_INT 1 "vsx_register_operand" "wa")))] + "TARGET_MMA && TARGET_VECTOR_SIZE_32" + "#" + "&& reload_completed" + [(const_int 0)] +{ + split_unary_vector_pair (<VPAIR_VECTOR>mode, operands, + gen_<vpair_op><vpair_vector>2); + DONE; +} + [(set_attr "length" "8")]) + +;; Vector pair negate if we have the VNEGx instruction. +(define_insn_and_split "neg<mode>2" + [(set (match_operand:VPAIR_NEG_VNEG 0 "vsx_register_operand" "=v") + (neg:VPAIR_NEG_VNEG + (match_operand:VPAIR_NEG_VNEG 1 "vsx_register_operand" "v")))] + "TARGET_MMA && TARGET_VECTOR_SIZE_32" + "#" + "&& reload_completed" + [(const_int 0)] +{ + split_unary_vector_pair (<VPAIR_VECTOR>mode, operands, + gen_neg<vpair_vector>2); + DONE; +} + [(set_attr "length" "8")]) + +;; Vector pair negate if we have to do a subtract from 0 +(define_insn_and_split "neg<mode>2" + [(set (match_operand:VPAIR_NEG_SUB 0 "vsx_register_operand" "=v") + (neg:VPAIR_NEG_SUB + (match_operand:VPAIR_NEG_SUB 1 "vsx_register_operand" "v"))) + (clobber (match_scratch:<VPAIR_VECTOR> 2 "=&v"))] + "TARGET_MMA && TARGET_VECTOR_SIZE_32" + "#" + "&& reload_completed" + [(const_int 0)] +{ + enum machine_mode mode = <VPAIR_VECTOR>mode; + rtx tmp = operands[2]; + unsigned reg0 = reg_or_subregno (operands[0]); + unsigned reg1 = reg_or_subregno (operands[1]); + + emit_move_insn (tmp, CONST0_RTX (mode)); + emit_insn (gen_sub<vpair_vector>3 (gen_rtx_REG (mode, reg0), + tmp, + gen_rtx_REG (mode, reg1))); + + emit_insn (gen_sub<vpair_vector>3 (gen_rtx_REG (mode, reg0 + 1), + tmp, + gen_rtx_REG (mode, reg1 + 1))); + + DONE; +} + [(set_attr "length" "8")]) + +;; Vector pair integer arithmetic binary operations +(define_insn_and_split "<vpair_op><mode>3" + [(set (match_operand:VPAIR_INT 0 "vsx_register_operand" "=v") + (VPAIR_INT_BINARY:VPAIR_INT + (match_operand:VPAIR_INT 1 "vsx_register_operand" "v") + (match_operand:VPAIR_INT 2 "vsx_register_operand" "v")))] + "TARGET_MMA && TARGET_VECTOR_SIZE_32" + "#" + "&& reload_completed" + [(const_int 0)] +{ + split_binary_vector_pair (<VPAIR_VECTOR>mode, operands, + gen_<vpair_op><vpair_vector>3); + DONE; +} + [(set_attr "length" "8")]) + +;; Vector pair integer arithmetic logical operations +(define_insn_and_split "<vpair_op><mode>3" + [(set (match_operand:VPAIR_INT 0 "vsx_register_operand" "=wa") + (VPAIR_INT_LOGICAL:VPAIR_INT + (match_operand:VPAIR_INT 1 "vsx_register_operand" "wa") + (match_operand:VPAIR_INT 2 "vsx_register_operand" "wa")))] + "TARGET_MMA && TARGET_VECTOR_SIZE_32" + "#" + "&& reload_completed" + [(const_int 0)] +{ + split_binary_vector_pair (<VPAIR_VECTOR>mode, operands, + gen_<vpair_op><vpair_vector>3); + DONE; +} + [(set_attr "length" "8")]) + +;; Optiomize vector pair ~(a | b) or ((~a) & (~b)) to produce xxlnor +(define_insn_and_split "*nor<mode>3_1" + [(set (match_operand:VPAIR_INT 0 "vsx_register_operand" "=wa") + (not:VPAIR_INT + (ior:VPAIR_INT + (match_operand:VPAIR_INT 1 "vsx_register_operand" "wa") + (match_operand:VPAIR_INT 2 "vsx_register_operand" "wa"))))] + "TARGET_MMA && TARGET_VECTOR_SIZE_32" + "#" + "&& reload_completed" + [(const_int 0)] +{ + split_binary_vector_pair (<VPAIR_VECTOR>mode, operands, + gen_nor<vpair_vector>3); + DONE; +} + [(set_attr "length" "8")]) + +(define_insn_and_split "*nor<mode>3_2" + [(set (match_operand:VPAIR_INT 0 "vsx_register_operand" "=wa") + (and:VPAIR_INT + (not:VPAIR_INT + (match_operand:VPAIR_INT 1 "vsx_register_operand" "wa")) + (not:VPAIR_INT + (match_operand:VPAIR_INT 2 "vsx_register_operand" "wa"))))] + "TARGET_MMA && TARGET_VECTOR_SIZE_32" + "#" + "&& reload_completed" + [(const_int 0)] +{ + split_binary_vector_pair (<VPAIR_VECTOR>mode, operands, + gen_nor<vpair_vector>3); + DONE; +} + [(set_attr "length" "8")]) + +;; Optimize vector pair (~a) & b to use xxlandc +(define_insn_and_split "*andc<mode>3" + [(set (match_operand:VPAIR_INT 0 "vsx_register_operand" "=wa") + (and:VPAIR_INT + (not:VPAIR_INT + (match_operand:VPAIR_INT 1 "vsx_register_operand" "wa")) + (match_operand:VPAIR_INT 2 "vsx_register_operand" "wa")))] + "TARGET_MMA && TARGET_VECTOR_SIZE_32" + "#" + "&& reload_completed" + [(const_int 0)] +{ + split_binary_vector_pair (<VPAIR_VECTOR>mode, operands, + gen_andc<vpair_vector>3); + DONE; +} + [(set_attr "length" "8")]) + +;; Optimize vector pair ~(a ^ b) to produce xxleqv +(define_insn_and_split "*eqv<mode>3" + [(set (match_operand:VPAIR_INT 0 "vsx_register_operand" "=wa") + (not:VPAIR_INT + (xor:VPAIR_INT + (match_operand:VPAIR_INT 1 "vsx_register_operand" "wa") + (match_operand:VPAIR_INT 2 "vsx_register_operand" "wa"))))] + "TARGET_MMA && TARGET_VECTOR_SIZE_32" + "#" + "&& reload_completed" + [(const_int 0)] +{ + split_binary_vector_pair (<VPAIR_VECTOR>mode, operands, + gen_nor<vpair_vector>3); + DONE; +} +[(set_attr "length" "8")]) + + +;; Optiomize vector pair ~(a & b) or ((~a) | (~b)) to produce xxlnand +(define_insn_and_split "*nand<mode>3_1" + [(set (match_operand:VPAIR_INT 0 "vsx_register_operand" "=wa") + (not:VPAIR_INT + (and:VPAIR_INT + (match_operand:VPAIR_INT 1 "vsx_register_operand" "wa") + (match_operand:VPAIR_INT 2 "vsx_register_operand" "wa"))))] + "TARGET_MMA && TARGET_VECTOR_SIZE_32" + "#" + "&& reload_completed" + [(const_int 0)] +{ + split_binary_vector_pair (<VPAIR_VECTOR>mode, operands, + gen_nand<vpair_vector>3); + DONE; +} + [(set_attr "length" "8")]) + +(define_insn_and_split "*nand<mode>3_2" + [(set (match_operand:VPAIR_INT 0 "vsx_register_operand" "=wa") + (ior:VPAIR_INT + (not:VPAIR_INT + (match_operand:VPAIR_INT 1 "vsx_register_operand" "wa")) + (not:VPAIR_INT + (match_operand:VPAIR_INT 2 "vsx_register_operand" "wa"))))] + "TARGET_MMA && TARGET_VECTOR_SIZE_32" + "#" + "&& reload_completed" + [(const_int 0)] +{ + split_binary_vector_pair (<VPAIR_VECTOR>mode, operands, + gen_nand<vpair_vector>3); + DONE; +} + [(set_attr "length" "8")]) + +;; Optimize vector pair (~a) | b to produce xxlorc +(define_insn_and_split "*orc<mode>3" + [(set (match_operand:VPAIR_INT 0 "vsx_register_operand" "=wa") + (ior:VPAIR_INT + (not:VPAIR_INT + (match_operand:VPAIR_INT 1 "vsx_register_operand" "wa")) + (match_operand:VPAIR_INT 2 "vsx_register_operand" "wa")))] + "TARGET_MMA && TARGET_VECTOR_SIZE_32" + "#" + "&& reload_completed" + [(const_int 0)] +{ + split_binary_vector_pair (<VPAIR_VECTOR>mode, operands, + gen_orc<vpair_vector>3); + DONE; +} + [(set_attr "length" "8")]) diff --git a/gcc/testsuite/gcc.target/powerpc/vector-size-32-1.c b/gcc/testsuite/gcc.target/powerpc/vector-size-32-1.c new file mode 100644 index 00000000000..89343c44a34 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vector-size-32-1.c @@ -0,0 +1,85 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target power10_ok } */ +/* { dg-options "-mdejagnu-cpu=power10 -O2 -mvector-size-32" } */ + +/* Test whether the __attrbiute__((__vector_size(32))) generates paired vector + loads and stores with the -mvector-size-32 option. This file tests 32-byte + vectors with 4 double elements. */ + +typedef double vectype_t __attribute__((__vector_size__(32))); + +void +test_add (vectype_t *dest, + vectype_t *a, + vectype_t *b) +{ + /* 2 lxvp, 2 xvadddp, 1 stxvp. */ + *dest = *a + *b; +} + +void +test_sub (vectype_t *dest, + vectype_t *a, + vectype_t *b) +{ + /* 2 lxvp, 2 xvsubdp, 1 stxvp. */ + *dest = *a - *b; +} + +void +test_multiply (vectype_t *dest, + vectype_t *a, + vectype_t *b) +{ + /* 2 lxvp, 2 xvmuldp, 1 stxvp. */ + *dest = *a * *b; +} + +void +test_negate (vectype_t *dest, + vectype_t *a, + vectype_t *b) +{ + /* 2 lxvp, 2 xvnegdp, 1 stxvp. */ + *dest = - *a; +} + +void +test_fma (vectype_t *dest, + vectype_t *a, + vectype_t *b, + vectype_t *c) +{ + /* 2 lxvp, 2 xvmadd{a,m}dp, 1 stxvp. */ + *dest = (*a * *b) + *c; +} + +void +test_fms (vectype_t *dest, + vectype_t *a, + vectype_t *b, + vectype_t *c) +{ + /* 2 lxvp, 2 xvmsub{a,m}dp, 1 stxvp. */ + *dest = (*a * *b) - *c; +} + +void +test_nfma (vectype_t *dest, + vectype_t *a, + vectype_t *b, + vectype_t *c) +{ + /* 2 lxvp, 2 xvnmadddp, 1 stxvp. */ + *dest = -((*a * *b) + *c); +} + +void +test_nfms (vectype_t *dest, + vectype_t *a, + vectype_t *b, + vectype_t *c) +{ + /* 2 lxvp, 2 xvnmsubdp, 1 stxvp. */ + *dest = -((*a * *b) - *c); +} diff --git a/gcc/testsuite/gcc.target/powerpc/vector-size-32-2.c b/gcc/testsuite/gcc.target/powerpc/vector-size-32-2.c new file mode 100644 index 00000000000..c598f6307d0 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vector-size-32-2.c @@ -0,0 +1,96 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target power10_ok } */ +/* { dg-options "-mdejagnu-cpu=power10 -O2 -mvector-size-32" } */ + +/* Test whether the __attrbiute__((__vector_size(32))) generates paired vector + loads and stores with the -mvector-size-32 option. This file tests 32-byte + vectors with 8 float elements. */ + +typedef float vectype_t __attribute__((__vector_size__(32))); + +void +test_add (vectype_t *dest, + vectype_t *a, + vectype_t *b) +{ + /* 2 lxvp, 2 xvaddsp, 1 stxvp. */ + *dest = *a + *b; +} + +void +test_sub (vectype_t *dest, + vectype_t *a, + vectype_t *b) +{ + /* 2 lxvp, 2 xvsubsp, 1 stxvp. */ + *dest = *a - *b; +} + +void +test_multiply (vectype_t *dest, + vectype_t *a, + vectype_t *b) +{ + /* 2 lxvp, 2 xvmulsp, 1 stxvp. */ + *dest = *a * *b; +} + +void +test_negate (vectype_t *dest, + vectype_t *a, + vectype_t *b) +{ + /* 2 lxvp, 2 xvnegsp, 1 stxvp. */ + *dest = - *a; +} + +void +test_fma (vectype_t *dest, + vectype_t *a, + vectype_t *b, + vectype_t *c) +{ + /* 2 lxvp, 2 xvmadd{a,m}sp, 1 stxvp. */ + *dest = (*a * *b) + *c; +} + +void +test_fms (vectype_t *dest, + vectype_t *a, + vectype_t *b, + vectype_t *c) +{ + /* 2 lxvp, 2 xvmsub{a,m}sp, 1 stxvp. */ + *dest = (*a * *b) - *c; +} + +void +test_nfma (vectype_t *dest, + vectype_t *a, + vectype_t *b, + vectype_t *c) +{ + /* 2 lxvp, 2 xvnmaddsp, 1 stxvp. */ + *dest = -((*a * *b) + *c); +} + +void +test_nfms (vectype_t *dest, + vectype_t *a, + vectype_t *b, + vectype_t *c) +{ + /* 2 lxvp, 2 xvnmsubsp, 1 stxvp. */ + *dest = -((*a * *b) - *c); +} + +/* { dg-final { scan-assembler-times {\mlxvp\M} 19 } } */ +/* { dg-final { scan-assembler-times {\mstxvp\M} 8 } } */ +/* { dg-final { scan-assembler-times {\mxvaddsp\M} 2 } } */ +/* { dg-final { scan-assembler-times {\mxvmadd.sp\M} 2 } } */ +/* { dg-final { scan-assembler-times {\mxvmsub.sp\M} 2 } } */ +/* { dg-final { scan-assembler-times {\mxvmulsp\M} 2 } } */ +/* { dg-final { scan-assembler-times {\mxvnegsp\M} 2 } } */ +/* { dg-final { scan-assembler-times {\mxvnmadd.sp\M} 2 } } */ +/* { dg-final { scan-assembler-times {\mxvnmsub.sp\M} 2 } } */ +/* { dg-final { scan-assembler-times {\mxvsubsp\M} 2 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vector-size-32-3.c b/gcc/testsuite/gcc.target/powerpc/vector-size-32-3.c new file mode 100644 index 00000000000..b1952b046f9 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vector-size-32-3.c @@ -0,0 +1,137 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target power10_ok } */ +/* { dg-options "-mdejagnu-cpu=power10 -O2 -mvector-size-32" } */ + +/* Test whether the __attrbiute__((__vector_size(32))) generates paired vector + loads and stores with the -mvector-size-32 option. This file tests 32-byte + vectors with 4 64-bit integer elements. */ + +typedef long long vectype_t __attribute__((__vector_size__(32))); + +void +test_add (vectype_t *dest, + vectype_t *a, + vectype_t *b) +{ + /* 2 lxvp, 2 vaddudm, 1 stxvp. */ + *dest = *a + *b; +} + +void +test_sub (vectype_t *dest, + vectype_t *a, + vectype_t *b) +{ + /* 2 lxvp, 2 vsubudm, 1 stxvp. */ + *dest = *a - *b; +} + +void +test_negate (vectype_t *dest, + vectype_t *a) +{ + /* 2 lxvp, 2 vnegd, 1 stxvp. */ + *dest = - *a; +} + +void +test_not (vectype_t *dest, + vectype_t *a) +{ + /* 2 lxvp, 2 xxlnor, 1 stxvp. */ + *dest = ~ *a; +} + +void +test_and (vectype_t *dest, + vectype_t *a, + vectype_t *b) +{ + /* 2 lxvp, 2 xxland, 1 stxvp. */ + *dest = *a & *b; +} + +void +test_or (vectype_t *dest, + vectype_t *a, + vectype_t *b) +{ + /* 2 lxvp, 2 xxlor, 1 stxvp. */ + *dest = *a | *b; +} + +void +test_xor (vectype_t *dest, + vectype_t *a, + vectype_t *b) +{ + /* 2 lxvp, 2 xxlxor, 1 stxvp. */ + *dest = *a ^ *b; +} + +void +test_andc_1 (vectype_t *dest, + vectype_t *a, + vectype_t *b) +{ + /* 2 lxvp, 2 xxlandc, 1 stxvp. */ + *dest = (~ *a) & *b; +} + +void +test_andc_2 (vectype_t *dest, + vectype_t *a, + vectype_t *b) +{ + /* 2 lxvp, 2 xxlandc, 1 stxvp. */ + *dest = *a & (~ *b); +} + +void +test_orc_1 (vectype_t *dest, + vectype_t *a, + vectype_t *b) +{ + /* 2 lxvp, 2 xxlorc, 1 stxvp. */ + *dest = (~ *a) | *b; +} + +void +test_orc_2 (vectype_t *dest, + vectype_t *a, + vectype_t *b) +{ + /* 2 lxvp, 2 xxlorc, 1 stxvp. */ + *dest = *a | (~ *b); +} + +void +test_nand (vectype_t *dest, + vectype_t *a, + vectype_t *b) +{ + /* 2 lxvp, 2 xxlnand, 1 stxvp. */ + *dest = ~(*a & *b); +} + +void +test_nor (vectype_t *dest, + vectype_t *a, + vectype_t *b) +{ + /* 2 lxvp, 2 xxlnor, 1 stxvp. */ + *dest = ~(*a | *b); +} + +/* { dg-final { scan-assembler-times {\mlxvp\M} 24 } } */ +/* { dg-final { scan-assembler-times {\mstxvp\M} 13 } } */ +/* { dg-final { scan-assembler-times {\mvaddudm\M} 2 } } */ +/* { dg-final { scan-assembler-times {\mvnegd\M} 2 } } */ +/* { dg-final { scan-assembler-times {\mvsubudm\M} 2 } } */ +/* { dg-final { scan-assembler-times {\mxxland\M} 2 } } */ +/* { dg-final { scan-assembler-times {\mxxlandc\M} 4 } } */ +/* { dg-final { scan-assembler-times {\mxxlnand\M} 2 } } */ +/* { dg-final { scan-assembler-times {\mxxlnor\M} 4 } } */ +/* { dg-final { scan-assembler-times {\mxxlor\M} 2 } } */ +/* { dg-final { scan-assembler-times {\mxxlorc\M} 4 } } */ +/* { dg-final { scan-assembler-times {\mxxlxor\M} 2 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vector-size-32-4.c b/gcc/testsuite/gcc.target/powerpc/vector-size-32-4.c new file mode 100644 index 00000000000..110292bb4df --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vector-size-32-4.c @@ -0,0 +1,137 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target power10_ok } */ +/* { dg-options "-mdejagnu-cpu=power10 -O2 -mvector-size-32" } */ + +/* Test whether the __attrbiute__((__vector_size(32))) generates paired vector + loads and stores with the -mvector-size-32 option. This file tests 32-byte + vectors with 4 64-bit integer elements. */ + +typedef int vectype_t __attribute__((__vector_size__(32))); + +void +test_add (vectype_t *dest, + vectype_t *a, + vectype_t *b) +{ + /* 2 lxvp, 2 vadduwm, 1 stxvp. */ + *dest = *a + *b; +} + +void +test_sub (vectype_t *dest, + vectype_t *a, + vectype_t *b) +{ + /* 2 lxvp, 2 vsubuwm, 1 stxvp. */ + *dest = *a - *b; +} + +void +test_negate (vectype_t *dest, + vectype_t *a) +{ + /* 2 lxvp, 2 vnegw, 1 stxvp. */ + *dest = - *a; +} + +void +test_not (vectype_t *dest, + vectype_t *a) +{ + /* 2 lxvp, 2 xxlnor, 1 stxvp. */ + *dest = ~ *a; +} + +void +test_and (vectype_t *dest, + vectype_t *a, + vectype_t *b) +{ + /* 2 lxvp, 2 xxland, 1 stxvp. */ + *dest = *a & *b; +} + +void +test_or (vectype_t *dest, + vectype_t *a, + vectype_t *b) +{ + /* 2 lxvp, 2 xxlor, 1 stxvp. */ + *dest = *a | *b; +} + +void +test_xor (vectype_t *dest, + vectype_t *a, + vectype_t *b) +{ + /* 2 lxvp, 2 xxlxor, 1 stxvp. */ + *dest = *a ^ *b; +} + +void +test_andc_1 (vectype_t *dest, + vectype_t *a, + vectype_t *b) +{ + /* 2 lxvp, 2 xxlandc, 1 stxvp. */ + *dest = (~ *a) & *b; +} + +void +test_andc_2 (vectype_t *dest, + vectype_t *a, + vectype_t *b) +{ + /* 2 lxvp, 2 xxlandc, 1 stxvp. */ + *dest = *a & (~ *b); +} + +void +test_orc_1 (vectype_t *dest, + vectype_t *a, + vectype_t *b) +{ + /* 2 lxvp, 2 xxlorc, 1 stxvp. */ + *dest = (~ *a) | *b; +} + +void +test_orc_2 (vectype_t *dest, + vectype_t *a, + vectype_t *b) +{ + /* 2 lxvp, 2 xxlorc, 1 stxvp. */ + *dest = *a | (~ *b); +} + +void +test_nand (vectype_t *dest, + vectype_t *a, + vectype_t *b) +{ + /* 2 lxvp, 2 xxlnand, 1 stxvp. */ + *dest = ~(*a & *b); +} + +void +test_nor (vectype_t *dest, + vectype_t *a, + vectype_t *b) +{ + /* 2 lxvp, 2 xxlnor, 1 stxvp. */ + *dest = ~(*a | *b); +} + +/* { dg-final { scan-assembler-times {\mlxvp\M} 24 } } */ +/* { dg-final { scan-assembler-times {\mstxvp\M} 13 } } */ +/* { dg-final { scan-assembler-times {\mvadduwm\M} 2 } } */ +/* { dg-final { scan-assembler-times {\mvnegw\M} 2 } } */ +/* { dg-final { scan-assembler-times {\mvsubuwm\M} 2 } } */ +/* { dg-final { scan-assembler-times {\mxxland\M} 2 } } */ +/* { dg-final { scan-assembler-times {\mxxlandc\M} 4 } } */ +/* { dg-final { scan-assembler-times {\mxxlnand\M} 2 } } */ +/* { dg-final { scan-assembler-times {\mxxlnor\M} 4 } } */ +/* { dg-final { scan-assembler-times {\mxxlor\M} 2 } } */ +/* { dg-final { scan-assembler-times {\mxxlorc\M} 4 } } */ +/* { dg-final { scan-assembler-times {\mxxlxor\M} 2 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vector-size-32-5.c b/gcc/testsuite/gcc.target/powerpc/vector-size-32-5.c new file mode 100644 index 00000000000..8921b04c468 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vector-size-32-5.c @@ -0,0 +1,137 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target power10_ok } */ +/* { dg-options "-mdejagnu-cpu=power10 -O2 -mvector-size-32" } */ + +/* Test whether the __attrbiute__((__vector_size(32))) generates paired vector + loads and stores with the -mvector-size-32 option. This file tests 32-byte + vectors with 4 64-bit integer elements. */ + +typedef short vectype_t __attribute__((__vector_size__(32))); + +void +test_add (vectype_t *dest, + vectype_t *a, + vectype_t *b) +{ + /* 2 lxvp, 2 vadduhm, 1 stxvp. */ + *dest = *a + *b; +} + +void +test_sub (vectype_t *dest, + vectype_t *a, + vectype_t *b) +{ + /* 2 lxvp, 2 vsubuhm, 1 stxvp. */ + *dest = *a - *b; +} + +void +test_negate (vectype_t *dest, + vectype_t *a) +{ + /* 2 lxvp, 1 xxspltib, 2 vsubuhm, 1 stxvp. */ + *dest = - *a; +} + +void +test_not (vectype_t *dest, + vectype_t *a) +{ + /* 2 lxvp, 2 xxlnor, 1 stxvp. */ + *dest = ~ *a; +} + +void +test_and (vectype_t *dest, + vectype_t *a, + vectype_t *b) +{ + /* 2 lxvp, 2 xxland, 1 stxvp. */ + *dest = *a & *b; +} + +void +test_or (vectype_t *dest, + vectype_t *a, + vectype_t *b) +{ + /* 2 lxvp, 2 xxlor, 1 stxvp. */ + *dest = *a | *b; +} + +void +test_xor (vectype_t *dest, + vectype_t *a, + vectype_t *b) +{ + /* 2 lxvp, 2 xxlxor, 1 stxvp. */ + *dest = *a ^ *b; +} + +void +test_andc_1 (vectype_t *dest, + vectype_t *a, + vectype_t *b) +{ + /* 2 lxvp, 2 xxlandc, 1 stxvp. */ + *dest = (~ *a) & *b; +} + +void +test_andc_2 (vectype_t *dest, + vectype_t *a, + vectype_t *b) +{ + /* 2 lxvp, 2 xxlandc, 1 stxvp. */ + *dest = *a & (~ *b); +} + +void +test_orc_1 (vectype_t *dest, + vectype_t *a, + vectype_t *b) +{ + /* 2 lxvp, 2 xxlorc, 1 stxvp. */ + *dest = (~ *a) | *b; +} + +void +test_orc_2 (vectype_t *dest, + vectype_t *a, + vectype_t *b) +{ + /* 2 lxvp, 2 xxlorc, 1 stxvp. */ + *dest = *a | (~ *b); +} + +void +test_nand (vectype_t *dest, + vectype_t *a, + vectype_t *b) +{ + /* 2 lxvp, 2 xxlnand, 1 stxvp. */ + *dest = ~(*a & *b); +} + +void +test_nor (vectype_t *dest, + vectype_t *a, + vectype_t *b) +{ + /* 2 lxvp, 2 xxlnor, 1 stxvp. */ + *dest = ~(*a | *b); +} + +/* { dg-final { scan-assembler-times {\mlxvp\M} 24 } } */ +/* { dg-final { scan-assembler-times {\mstxvp\M} 13 } } */ +/* { dg-final { scan-assembler-times {\mvadduhm\M} 2 } } */ +/* { dg-final { scan-assembler-times {\mvsubuhm\M} 4 } } */ +/* { dg-final { scan-assembler-times {\mxxland\M} 2 } } */ +/* { dg-final { scan-assembler-times {\mxxlandc\M} 4 } } */ +/* { dg-final { scan-assembler-times {\mxxlnand\M} 2 } } */ +/* { dg-final { scan-assembler-times {\mxxlnor\M} 4 } } */ +/* { dg-final { scan-assembler-times {\mxxlor\M} 2 } } */ +/* { dg-final { scan-assembler-times {\mxxlorc\M} 4 } } */ +/* { dg-final { scan-assembler-times {\mxxlxor\M} 2 } } */ +/* { dg-final { scan-assembler-times {\mxxspltib\M} 1 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vector-size-32-6.c b/gcc/testsuite/gcc.target/powerpc/vector-size-32-6.c new file mode 100644 index 00000000000..a905e6b0a31 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vector-size-32-6.c @@ -0,0 +1,137 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target power10_ok } */ +/* { dg-options "-mdejagnu-cpu=power10 -O2 -mvector-size-32" } */ + +/* Test whether the __attrbiute__((__vector_size(32))) generates paired vector + loads and stores with the -mvector-size-32 option. This file tests 32-byte + vectors with 4 64-bit integer elements. */ + +typedef unsigned char vectype_t __attribute__((__vector_size__(32))); + +void +test_add (vectype_t *dest, + vectype_t *a, + vectype_t *b) +{ + /* 2 lxvp, 2 vaddubm, 1 stxvp. */ + *dest = *a + *b; +} + +void +test_sub (vectype_t *dest, + vectype_t *a, + vectype_t *b) +{ + /* 2 lxvp, 2 vsububm, 1 stxvp. */ + *dest = *a - *b; +} + +void +test_negate (vectype_t *dest, + vectype_t *a) +{ + /* 2 lxvp, 1 xxspltib, 2 vsububm, 1 stxvp. */ + *dest = - *a; +} + +void +test_not (vectype_t *dest, + vectype_t *a) +{ + /* 2 lxvp, 2 xxlnor, 1 stxvp. */ + *dest = ~ *a; +} + +void +test_and (vectype_t *dest, + vectype_t *a, + vectype_t *b) +{ + /* 2 lxvp, 2 xxland, 1 stxvp. */ + *dest = *a & *b; +} + +void +test_or (vectype_t *dest, + vectype_t *a, + vectype_t *b) +{ + /* 2 lxvp, 2 xxlor, 1 stxvp. */ + *dest = *a | *b; +} + +void +test_xor (vectype_t *dest, + vectype_t *a, + vectype_t *b) +{ + /* 2 lxvp, 2 xxlxor, 1 stxvp. */ + *dest = *a ^ *b; +} + +void +test_andc_1 (vectype_t *dest, + vectype_t *a, + vectype_t *b) +{ + /* 2 lxvp, 2 xxlandc, 1 stxvp. */ + *dest = (~ *a) & *b; +} + +void +test_andc_2 (vectype_t *dest, + vectype_t *a, + vectype_t *b) +{ + /* 2 lxvp, 2 xxlandc, 1 stxvp. */ + *dest = *a & (~ *b); +} + +void +test_orc_1 (vectype_t *dest, + vectype_t *a, + vectype_t *b) +{ + /* 2 lxvp, 2 xxlorc, 1 stxvp. */ + *dest = (~ *a) | *b; +} + +void +test_orc_2 (vectype_t *dest, + vectype_t *a, + vectype_t *b) +{ + /* 2 lxvp, 2 xxlorc, 1 stxvp. */ + *dest = *a | (~ *b); +} + +void +test_nand (vectype_t *dest, + vectype_t *a, + vectype_t *b) +{ + /* 2 lxvp, 2 xxlnand, 1 stxvp. */ + *dest = ~(*a & *b); +} + +void +test_nor (vectype_t *dest, + vectype_t *a, + vectype_t *b) +{ + /* 2 lxvp, 2 xxlnor, 1 stxvp. */ + *dest = ~(*a | *b); +} + +/* { dg-final { scan-assembler-times {\mlxvp\M} 24 } } */ +/* { dg-final { scan-assembler-times {\mstxvp\M} 13 } } */ +/* { dg-final { scan-assembler-times {\mvaddubm\M} 2 } } */ +/* { dg-final { scan-assembler-times {\mvsububm\M} 4 } } */ +/* { dg-final { scan-assembler-times {\mxxland\M} 2 } } */ +/* { dg-final { scan-assembler-times {\mxxlandc\M} 4 } } */ +/* { dg-final { scan-assembler-times {\mxxlnand\M} 2 } } */ +/* { dg-final { scan-assembler-times {\mxxlnor\M} 4 } } */ +/* { dg-final { scan-assembler-times {\mxxlor\M} 2 } } */ +/* { dg-final { scan-assembler-times {\mxxlorc\M} 4 } } */ +/* { dg-final { scan-assembler-times {\mxxlxor\M} 2 } } */ +/* { dg-final { scan-assembler-times {\mxxspltib\M} 1 } } */
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