From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1005) id A4B3D3858C52; Fri, 29 Sep 2023 05:46:26 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org A4B3D3858C52 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1695966386; bh=QxmmQKdBjtdc+EU87mqM8T1CKtaJbXq0x7dIhEWU21A=; h=From:To:Subject:Date:From; b=syM+T2O3WPJsGiCjYmwopaP3DzvuN82I6wcP6/vdtfKZJrN4evOFOyvYCIjK//hpG 8HOkzuktfUYPmF5AsmX2i8BvQCZ1LaPERSabfpZywtTM6sPFeTFHi3xB32Z9XO8G9K 4paSvVy1eR8XgKe2H9rS9nq0shF4LWCrRP1g4/kg= Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Michael Meissner To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/users/meissner/heads/work137-vsubreg)] Peter's patches for subreg support. X-Act-Checkin: gcc X-Git-Author: Michael Meissner X-Git-Refname: refs/users/meissner/heads/work137-vsubreg X-Git-Oldrev: a4c2b7845e63d0014ac300317fef83383e16264b X-Git-Newrev: 0eb03e85dccc79a68800150dd894a68af10dd187 Message-Id: <20230929054626.A4B3D3858C52@sourceware.org> Date: Fri, 29 Sep 2023 05:46:26 +0000 (GMT) List-Id: https://gcc.gnu.org/g:0eb03e85dccc79a68800150dd894a68af10dd187 commit 0eb03e85dccc79a68800150dd894a68af10dd187 Author: Michael Meissner Date: Fri Sep 29 01:44:28 2023 -0400 Peter's patches for subreg support. 2023-09-21 Peter Bergner gcc/ PR target/109116 * gcc/config/rs6000/rs6000.cc (rs6000_modes_tieable_p): Make OOmdoe tieable with 128-bit vector modes. 2023-09-15 Peter Bergner gcc/ PR target/109116 * gcc/config/rs6000/mma.md (vsx_disassemble_pair): Use SUBREG's instead of UNSPEC's. (mma_disassemble_acc): Likewise. Diff: --- gcc/config/rs6000/mma.md | 50 ++++----------------------------------------- gcc/config/rs6000/rs6000.cc | 9 +++++--- 2 files changed, 10 insertions(+), 49 deletions(-) diff --git a/gcc/config/rs6000/mma.md b/gcc/config/rs6000/mma.md index b6cc7b28956..470dc2cca3a 100644 --- a/gcc/config/rs6000/mma.md +++ b/gcc/config/rs6000/mma.md @@ -405,29 +405,8 @@ (match_operand 2 "const_0_to_1_operand")] "TARGET_MMA" { - rtx src; - int regoff = INTVAL (operands[2]); - src = gen_rtx_UNSPEC (V16QImode, - gen_rtvec (2, operands[1], GEN_INT (regoff)), - UNSPEC_MMA_EXTRACT); - emit_move_insn (operands[0], src); - DONE; -}) - -(define_insn_and_split "*vsx_disassemble_pair" - [(set (match_operand:V16QI 0 "mma_disassemble_output_operand" "=mwa") - (unspec:V16QI [(match_operand:OO 1 "vsx_register_operand" "wa") - (match_operand 2 "const_0_to_1_operand")] - UNSPEC_MMA_EXTRACT))] - "TARGET_MMA - && vsx_register_operand (operands[1], OOmode)" - "#" - "&& reload_completed" - [(const_int 0)] -{ - int reg = REGNO (operands[1]); - int regoff = INTVAL (operands[2]); - rtx src = gen_rtx_REG (V16QImode, reg + regoff); + int regoff = INTVAL (operands[2]) * GET_MODE_SIZE (V16QImode); + rtx src = simplify_gen_subreg (V16QImode, operands[1], OOmode, regoff); emit_move_insn (operands[0], src); DONE; }) @@ -479,29 +458,8 @@ (match_operand 2 "const_0_to_3_operand")] "TARGET_MMA" { - rtx src; - int regoff = INTVAL (operands[2]); - src = gen_rtx_UNSPEC (V16QImode, - gen_rtvec (2, operands[1], GEN_INT (regoff)), - UNSPEC_MMA_EXTRACT); - emit_move_insn (operands[0], src); - DONE; -}) - -(define_insn_and_split "*mma_disassemble_acc" - [(set (match_operand:V16QI 0 "mma_disassemble_output_operand" "=mwa") - (unspec:V16QI [(match_operand:XO 1 "fpr_reg_operand" "d") - (match_operand 2 "const_0_to_3_operand")] - UNSPEC_MMA_EXTRACT))] - "TARGET_MMA - && fpr_reg_operand (operands[1], XOmode)" - "#" - "&& reload_completed" - [(const_int 0)] -{ - int reg = REGNO (operands[1]); - int regoff = INTVAL (operands[2]); - rtx src = gen_rtx_REG (V16QImode, reg + regoff); + int regoff = INTVAL (operands[2]) * GET_MODE_SIZE (V16QImode); + rtx src = simplify_gen_subreg (V16QImode, operands[1], XOmode, regoff); emit_move_insn (operands[0], src); DONE; }) diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc index ae7d7dbd621..3c6d7d86f5b 100644 --- a/gcc/config/rs6000/rs6000.cc +++ b/gcc/config/rs6000/rs6000.cc @@ -1964,9 +1964,12 @@ rs6000_hard_regno_mode_ok (unsigned int regno, machine_mode mode) static bool rs6000_modes_tieable_p (machine_mode mode1, machine_mode mode2) { - if (mode1 == PTImode || mode1 == OOmode || mode1 == XOmode - || mode2 == PTImode || mode2 == OOmode || mode2 == XOmode) - return mode1 == mode2; + if (mode1 == PTImode || mode1 == OOmode || mode1 == XOmode + || mode2 == PTImode || mode2 == XOmode) + return mode1 == mode2; + + if (mode2 == OOmode) + return ALTIVEC_OR_VSX_VECTOR_MODE (mode1); if (ALTIVEC_OR_VSX_VECTOR_MODE (mode1)) return ALTIVEC_OR_VSX_VECTOR_MODE (mode2);