From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1118) id 3FD883858C78; Fri, 29 Sep 2023 15:41:58 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 3FD883858C78 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1696002118; bh=5gMSaLLLq5INv7tfHNfLJBwQ+utR7UG86Z4JIwKS0LU=; h=From:To:Subject:Date:From; b=qbjXms9HdKaPMqbdsUxyf8O15Uc4OhLL/BzMbJRi8QnrNOvyMyvKq7KqI0F6Xvo8a XPtgukcdbo8XP74MzgX5GcOKiR+9w6OhSILh7BUpJ3+zdqC3XIn8VXhr0r98ZtOhsy d+hcHRnCvM6PpAKPbHUHWH0hk4GTW8BTTNvap7d0= MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="utf-8" From: John David Anglin To: gcc-cvs@gcc.gnu.org Subject: [gcc r14-4336] Fix memory barrier patterns for pre PA8800 processors X-Act-Checkin: gcc X-Git-Author: John David Anglin X-Git-Refname: refs/heads/master X-Git-Oldrev: a8b9c32da787ea0bfbfc9118ac816fa7be4b1bc8 X-Git-Newrev: 0f184b4141e9d285c19b3a3d02bffa45bc0d8f07 Message-Id: <20230929154158.3FD883858C78@sourceware.org> Date: Fri, 29 Sep 2023 15:41:58 +0000 (GMT) List-Id: https://gcc.gnu.org/g:0f184b4141e9d285c19b3a3d02bffa45bc0d8f07 commit r14-4336-g0f184b4141e9d285c19b3a3d02bffa45bc0d8f07 Author: John David Anglin Date: Fri Sep 29 15:37:44 2023 +0000 Fix memory barrier patterns for pre PA8800 processors 2023-09-29 John David Anglin * config/pa/pa.md (memory_barrier): Revise comment. (memory_barrier_64, memory_barrier_32): Use ldcw,co on PA 2.0. * config/pa/pa.opt (coherent-ldcw): Change default to disabled. Diff: --- gcc/config/pa/pa.md | 12 ++++++------ gcc/config/pa/pa.opt | 2 +- 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/gcc/config/pa/pa.md b/gcc/config/pa/pa.md index f603591447d..4f85991e6bd 100644 --- a/gcc/config/pa/pa.md +++ b/gcc/config/pa/pa.md @@ -10739,10 +10739,10 @@ add,l %2,%3,%3\;bv,n %%r0(%3)" ;; generating PA 1.x code even though all PA 1.x systems are strongly ordered. ;; When barriers are needed, we use a strongly ordered ldcw instruction as -;; the barrier. Most PA 2.0 targets are cache coherent. In that case, we -;; can use the coherent cache control hint and avoid aligning the ldcw -;; address. In spite of its description, it is not clear that the sync -;; instruction works as a barrier. +;; the barrier. All PA 2.0 targets accept the "co" cache control hint but +;; only PA8800 and PA8900 processors implement the cacheable hint. In +;; that case, we can avoid aligning the ldcw address. In spite of its +;; description, it is not clear that the sync instruction works as a barrier. (define_expand "memory_barrier" [(parallel @@ -10772,7 +10772,7 @@ add,l %2,%3,%3\;bv,n %%r0(%3)" (unspec:BLK [(match_dup 0)] UNSPEC_MEMORY_BARRIER)) (clobber (match_operand 1 "pmode_register_operand" "=&r"))] "TARGET_64BIT" - "ldo 15(%%sp),%1\n\tdepd %%r0,63,3,%1\n\tldcw 0(%1),%1" + "ldo 15(%%sp),%1\n\tdepd %%r0,63,3,%1\n\tldcw,co 0(%1),%1" [(set_attr "type" "binary") (set_attr "length" "12")]) @@ -10781,6 +10781,6 @@ add,l %2,%3,%3\;bv,n %%r0(%3)" (unspec:BLK [(match_dup 0)] UNSPEC_MEMORY_BARRIER)) (clobber (match_operand 1 "pmode_register_operand" "=&r"))] "" - "ldo 15(%%sp),%1\n\t{dep|depw} %%r0,31,3,%1\n\tldcw 0(%1),%1" + "ldo 15(%%sp),%1\n\t{dep|depw} %%r0,31,3,%1\n\t{ldcw|ldcw,co} 0(%1),%1" [(set_attr "type" "binary") (set_attr "length" "12")]) diff --git a/gcc/config/pa/pa.opt b/gcc/config/pa/pa.opt index dd358f2f26a..573edcea338 100644 --- a/gcc/config/pa/pa.opt +++ b/gcc/config/pa/pa.opt @@ -50,7 +50,7 @@ Target Mask(CALLER_COPIES) Caller copies function arguments passed by hidden reference. mcoherent-ldcw -Target Var(TARGET_COHERENT_LDCW) Init(1) +Target Var(TARGET_COHERENT_LDCW) Init(0) Use ldcw/ldcd coherent cache-control hint. mdisable-fpregs