From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 7924) id 238013858D28; Sat, 14 Oct 2023 03:42:25 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 238013858D28 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1697254945; bh=5b+dzCa3LVpj2r6bMacDh7370e2njq/tYHv+UXd/e9g=; h=From:To:Subject:Date:From; b=pG5ldtyi8c5n8Y5+XARg5SiZou9nO3ECgeEmTtaMX0wt7AWxgxLosWUrP3XJUMsia i1OIBgyNcM5ZYVMBKb2uPkye0Vrrb5ad4n8LUqskN3bUQkqJi6iDE3Iyo1VqBc5aRv BgczV6LXUjYhwNBhdUyobyVAAqSXri+NXhEC3f7Y= MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="utf-8" From: Pan Li To: gcc-cvs@gcc.gnu.org Subject: [gcc r14-4634] RISC-V: Remove redundant iterators. X-Act-Checkin: gcc X-Git-Author: Juzhe-Zhong X-Git-Refname: refs/heads/master X-Git-Oldrev: 300d7d3a8f4b53d045ce43f1ed4e10301781c786 X-Git-Newrev: 78dd49f387c515a6b28ef3fcb989605a168ff752 Message-Id: <20231014034225.238013858D28@sourceware.org> Date: Sat, 14 Oct 2023 03:42:25 +0000 (GMT) List-Id: https://gcc.gnu.org/g:78dd49f387c515a6b28ef3fcb989605a168ff752 commit r14-4634-g78dd49f387c515a6b28ef3fcb989605a168ff752 Author: Juzhe-Zhong Date: Sat Oct 14 11:06:02 2023 +0800 RISC-V: Remove redundant iterators. These iterators are redundant, removed and commmitted. gcc/ChangeLog: * config/riscv/vector-iterators.md: Remove redundant iterators. Diff: --- gcc/config/riscv/vector-iterators.md | 110 ----------------------------------- 1 file changed, 110 deletions(-) diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md index 96ddd34c958..6800f8d3d76 100644 --- a/gcc/config/riscv/vector-iterators.md +++ b/gcc/config/riscv/vector-iterators.md @@ -295,83 +295,6 @@ RVVM1QI RVVMF2QI RVVMF4QI (RVVMF8QI "TARGET_MIN_VLEN > 32") ]) -(define_mode_iterator VLMULEXT2 [ - RVVM4QI RVVM2QI RVVM1QI RVVMF2QI RVVMF4QI (RVVMF8QI "TARGET_MIN_VLEN > 32") - - RVVM4HI RVVM2HI RVVM1HI RVVMF2HI (RVVMF4HI "TARGET_MIN_VLEN > 32") - - (RVVM4HF "TARGET_VECTOR_ELEN_FP_16") (RVVM2HF "TARGET_VECTOR_ELEN_FP_16") - (RVVM1HF "TARGET_VECTOR_ELEN_FP_16") (RVVMF2HF "TARGET_VECTOR_ELEN_FP_16") - (RVVMF4HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32") - - RVVM4SI RVVM2SI RVVM1SI (RVVMF2SI "TARGET_MIN_VLEN > 32") - - (RVVM4SF "TARGET_VECTOR_ELEN_FP_32") (RVVM2SF "TARGET_VECTOR_ELEN_FP_32") - (RVVM1SF "TARGET_VECTOR_ELEN_FP_32") (RVVMF2SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32") - - (RVVM4DI "TARGET_VECTOR_ELEN_64") (RVVM2DI "TARGET_VECTOR_ELEN_64") (RVVM1DI "TARGET_VECTOR_ELEN_64") - - (RVVM4DF "TARGET_VECTOR_ELEN_FP_64") (RVVM2DF "TARGET_VECTOR_ELEN_FP_64") (RVVM1DF "TARGET_VECTOR_ELEN_FP_64") -]) - -(define_mode_iterator VLMULEXT4 [ - RVVM2QI RVVM1QI RVVMF2QI RVVMF4QI (RVVMF8QI "TARGET_MIN_VLEN > 32") - - RVVM2HI RVVM1HI RVVMF2HI (RVVMF4HI "TARGET_MIN_VLEN > 32") - - (RVVM2HF "TARGET_VECTOR_ELEN_FP_16") (RVVM1HF "TARGET_VECTOR_ELEN_FP_16") (RVVMF2HF "TARGET_VECTOR_ELEN_FP_16") - (RVVMF4HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32") - - RVVM2SI RVVM1SI (RVVMF2SI "TARGET_MIN_VLEN > 32") - - (RVVM2SF "TARGET_VECTOR_ELEN_FP_32") (RVVM1SF "TARGET_VECTOR_ELEN_FP_32") (RVVMF2SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32") - - (RVVM2DI "TARGET_VECTOR_ELEN_64") (RVVM1DI "TARGET_VECTOR_ELEN_64") - - (RVVM2DF "TARGET_VECTOR_ELEN_FP_64") (RVVM1DF "TARGET_VECTOR_ELEN_FP_64") -]) - -(define_mode_iterator VLMULEXT8 [ - RVVM1QI RVVMF2QI RVVMF4QI (RVVMF8QI "TARGET_MIN_VLEN > 32") - - RVVM1HI RVVMF2HI (RVVMF4HI "TARGET_MIN_VLEN > 32") - - (RVVM1HF "TARGET_VECTOR_ELEN_FP_16") (RVVMF2HF "TARGET_VECTOR_ELEN_FP_16") - (RVVMF4HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32") - - RVVM1SI (RVVMF2SI "TARGET_MIN_VLEN > 32") - - (RVVM1SF "TARGET_VECTOR_ELEN_FP_32") (RVVMF2SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32") - - (RVVM1DI "TARGET_VECTOR_ELEN_64") - - (RVVM1DF "TARGET_VECTOR_ELEN_FP_64") -]) - -(define_mode_iterator VLMULEXT16 [ - RVVMF2QI RVVMF4QI (RVVMF8QI "TARGET_MIN_VLEN > 32") - - RVVMF2HI (RVVMF4HI "TARGET_MIN_VLEN > 32") - - (RVVMF2HF "TARGET_VECTOR_ELEN_FP_16") (RVVMF4HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32") - - (RVVMF2SI "TARGET_MIN_VLEN > 32") - - (RVVMF2SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32") -]) - -(define_mode_iterator VLMULEXT32 [ - RVVMF4QI (RVVMF8QI "TARGET_MIN_VLEN > 32") - - (RVVMF4HI "TARGET_MIN_VLEN > 32") - - (RVVMF4HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32") -]) - -(define_mode_iterator VLMULEXT64 [ - (RVVMF8QI "TARGET_MIN_VLEN > 32") -]) - (define_mode_iterator VEI16 [ RVVM4QI RVVM2QI RVVM1QI RVVMF2QI RVVMF4QI (RVVMF8QI "TARGET_MIN_VLEN > 32") @@ -1579,39 +1502,6 @@ RVVM4x2QI ]) -(define_mode_iterator VQI [ - RVVM8QI RVVM4QI RVVM2QI RVVM1QI RVVMF2QI RVVMF4QI (RVVMF8QI "TARGET_MIN_VLEN > 32") -]) - -(define_mode_iterator VHI [ - RVVM8HI RVVM4HI RVVM2HI RVVM1HI RVVMF2HI (RVVMF4HI "TARGET_MIN_VLEN > 32") -]) - -(define_mode_iterator VSI [ - RVVM8SI RVVM4SI RVVM2SI RVVM1SI (RVVMF2SI "TARGET_MIN_VLEN > 32") -]) - -(define_mode_iterator VDI [ - (RVVM8DI "TARGET_VECTOR_ELEN_64") (RVVM4DI "TARGET_VECTOR_ELEN_64") - (RVVM2DI "TARGET_VECTOR_ELEN_64") (RVVM1DI "TARGET_VECTOR_ELEN_64") -]) - -(define_mode_iterator VHF [ - (RVVM8HF "TARGET_ZVFH") (RVVM4HF "TARGET_ZVFH") (RVVM2HF "TARGET_ZVFH") - (RVVM1HF "TARGET_ZVFH") (RVVMF2HF "TARGET_ZVFH") - (RVVMF4HF "TARGET_ZVFH && TARGET_MIN_VLEN > 32") -]) - -(define_mode_iterator VSF [ - (RVVM8SF "TARGET_VECTOR_ELEN_FP_32") (RVVM4SF "TARGET_VECTOR_ELEN_FP_32") (RVVM2SF "TARGET_VECTOR_ELEN_FP_32") - (RVVM1SF "TARGET_VECTOR_ELEN_FP_32") (RVVMF2SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32") -]) - -(define_mode_iterator VDF [ - (RVVM8DF "TARGET_VECTOR_ELEN_FP_64") (RVVM4DF "TARGET_VECTOR_ELEN_FP_64") - (RVVM2DF "TARGET_VECTOR_ELEN_FP_64") (RVVM1DF "TARGET_VECTOR_ELEN_FP_64") -]) - (define_mode_attr V_LMUL1 [ (RVVM8QI "RVVM1QI") (RVVM4QI "RVVM1QI") (RVVM2QI "RVVM1QI") (RVVM1QI "RVVM1QI") (RVVMF2QI "RVVM1QI") (RVVMF4QI "RVVM1QI") (RVVMF8QI "RVVM1QI")