From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 2078) id A06CC3858415; Mon, 16 Oct 2023 01:08:33 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org A06CC3858415 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1697418513; bh=GrR12LstssXHHvn+Je1g8yn1EshvSMZO1tfFpq52zWw=; h=From:To:Subject:Date:From; b=i5kIvJnDVHEza4ZX+c4hiOnyowssjfoHUUCi/3z2rxxWU3oikPrWsYoPkFgp7xhgb TFYy3DlznNWCXN1P3KNUFu+ueqjQEJtghah8bY2YFXPzzLLsGAYH2w0qgZXVYIBNzh 1RQ5e4zm/1iPaD1963bnpHI5af5C8QLo9lr8xj9w= MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="utf-8" From: hongtao Liu To: gcc-cvs@gcc.gnu.org Subject: [gcc r14-4654] Support 32/64-bit vectorization for conversion between _Float16 and integer/float. X-Act-Checkin: gcc X-Git-Author: liuhongt X-Git-Refname: refs/heads/master X-Git-Oldrev: 96f12b9f9b9646deb0f7678a3f8d544e8d48cb91 X-Git-Newrev: e6d063086726ccb2c5219611319285099a628878 Message-Id: <20231016010833.A06CC3858415@sourceware.org> Date: Mon, 16 Oct 2023 01:08:33 +0000 (GMT) List-Id: https://gcc.gnu.org/g:e6d063086726ccb2c5219611319285099a628878 commit r14-4654-ge6d063086726ccb2c5219611319285099a628878 Author: liuhongt Date: Wed Oct 11 17:14:47 2023 +0800 Support 32/64-bit vectorization for conversion between _Float16 and integer/float. gcc/ChangeLog: * config/i386/mmx.md (V2FI_32): New mode iterator (movd_v2hf_to_sse): Rename to .. (movd__to_sse): .. this. (movd_v2hf_to_sse_reg): Rename to .. (movd__to_sse_reg): .. this. (fix_trunc2): New expander. (fix_truncv2hfv2si2): Ditto. (float2): Ditto. (floatv2siv2hf2): Ditto. (extendv2hfv2sf2): Ditto. (truncv2sfv2hf2): Ditto. * config/i386/sse.md (*vec_concatv8hf_movss): Rename to .. (*vec_concat_movss): .. this. gcc/testsuite/ChangeLog: * gcc.target/i386/part-vect-hf-convert-1.c: New test. Diff: --- gcc/config/i386/mmx.md | 164 ++++++++++++++++++--- gcc/config/i386/sse.md | 12 +- .../gcc.target/i386/part-vect-hf-convert-1.c | 111 ++++++++++++++ 3 files changed, 262 insertions(+), 25 deletions(-) diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md index 91674b4675e..82ca49c207b 100644 --- a/gcc/config/i386/mmx.md +++ b/gcc/config/i386/mmx.md @@ -60,6 +60,7 @@ ;; All 4-byte integer/float16 vector modes (define_mode_iterator V_32 [V4QI V2HI V1SI V2HF V2BF]) +(define_mode_iterator V2FI_32 [V2HF V2BF V2HI]) ;; 4-byte integer vector modes (define_mode_iterator VI_32 [V4QI V2HI]) @@ -79,7 +80,7 @@ ;; V2S* modes (define_mode_iterator V2FI [V2SF V2SI]) -(define_mode_iterator V2FI_V4HF [V2SF V2SI V4HF]) +(define_mode_iterator V24FI [V2SF V2SI V4HF V4HI]) ;; Mapping from integer vector mode to mnemonic suffix (define_mode_attr mmxvecsize [(V8QI "b") (V4QI "b") (V2QI "b") @@ -100,7 +101,7 @@ ;; Mapping of vector float modes to an integer mode of the same size (define_mode_attr mmxintvecmode [(V2SF "V2SI") (V2SI "V2SI") (V4HI "V4HI") (V8QI "V8QI") - (V4HF "V4HF") (V2HF "V2HI")]) + (V4HF "V4HI") (V2HF "V2HI")]) (define_mode_attr mmxintvecmodelower [(V2SF "v2si") (V2SI "v2si") (V4HI "v4hi") (V8QI "v8qi") @@ -108,7 +109,7 @@ ;; Mapping of vector modes to a vector mode of double size (define_mode_attr mmxdoublevecmode - [(V2SF "V4SF") (V2SI "V4SI") (V4HF "V8HF")]) + [(V2SF "V4SF") (V2SI "V4SI") (V4HF "V8HF") (V4HI "V8HI")]) ;; Mapping of vector modes back to the scalar modes (define_mode_attr mmxscalarmode @@ -600,7 +601,7 @@ (define_expand "movq__to_sse" [(set (match_operand: 0 "register_operand") (vec_concat: - (match_operand:V2FI_V4HF 1 "nonimmediate_operand") + (match_operand:V24FI 1 "nonimmediate_operand") (match_dup 2)))] "TARGET_SSE2" { @@ -1967,31 +1968,40 @@ DONE; }) -(define_mode_attr mov_to_sse_suffix [(V2HF "d") (V4HF "q")]) -(define_expand "movd_v2hf_to_sse" - [(set (match_operand:V8HF 0 "register_operand") - (vec_merge:V8HF - (vec_duplicate:V8HF - (match_operand:V2HF 1 "nonimmediate_operand")) +(define_mode_attr mov_to_sse_suffix + [(V2HF "d") (V4HF "q") (V2HI "d") (V4HI "q")]) + +(define_mode_attr mmxxmmmode + [(V2HF "V8HF") (V2HI "V8HI") (V2BF "V8BF")]) + +(define_mode_attr mmxxmmmodelower + [(V2HF "v8hf") (V2HI "v8hi") (V2BF "v8bf")]) + +(define_expand "movd__to_sse" + [(set (match_operand: 0 "register_operand") + (vec_merge: + (vec_duplicate: + (match_operand:V2FI_32 1 "nonimmediate_operand")) (match_dup 2) (const_int 3)))] "TARGET_SSE" { if (!flag_trapping_math) { - rtx op1 = force_reg (V2HFmode, operands[1]); - emit_move_insn (operands[0], lowpart_subreg (V8HFmode, op1, V2HFmode)); + rtx op1 = force_reg (mode, operands[1]); + emit_move_insn (operands[0], + lowpart_subreg (mode, op1, mode)); DONE; } - operands[2] = CONST0_RTX (V8HFmode); + operands[2] = CONST0_RTX (mode); }) -(define_expand "movd_v2hf_to_sse_reg" - [(set (match_operand:V8HF 0 "register_operand") - (vec_merge:V8HF - (vec_duplicate:V8HF - (match_operand:V2HF 1 "nonimmediate_operand")) - (match_operand:V8HF 2 "register_operand") +(define_expand "movd__to_sse_reg" + [(set (match_operand: 0 "register_operand") + (vec_merge: + (vec_duplicate: + (match_operand:V2FI_32 1 "nonimmediate_operand")) + (match_operand: 2 "register_operand") (const_int 3)))] "TARGET_SSE") @@ -2353,6 +2363,122 @@ "TARGET_SSE2" "operands[2] = GEN_INT (GET_MODE_UNIT_BITSIZE (mode)-1);") +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Parallel single-precision floating point conversion operations +;; +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +(define_expand "fix_trunc2" + [(set (match_operand: 0 "register_operand") + (any_fix: + (match_operand:VHF_32_64 1 "nonimmediate_operand")))] + "TARGET_AVX512FP16 && TARGET_AVX512VL && ix86_partial_vec_fp_math" +{ + rtx op1 = gen_reg_rtx (V8HFmode); + rtx op0 = gen_reg_rtx (V8HImode); + + emit_insn (gen_mov__to_sse (op1, operands[1])); + + emit_insn (gen_fix_truncv8hfv8hi2 (op0, op1)); + + emit_move_insn (operands[0], + lowpart_subreg (mode, op0, V8HImode)); + DONE; +}) + +(define_expand "fix_truncv2hfv2si2" + [(set (match_operand:V2SI 0 "register_operand") + (any_fix:V2SI + (match_operand:V2HF 1 "nonimmediate_operand")))] + "TARGET_AVX512FP16 && TARGET_AVX512VL + && TARGET_MMX_WITH_SSE && ix86_partial_vec_fp_math" +{ + rtx op1 = gen_reg_rtx (V8HFmode); + rtx op0 = gen_reg_rtx (V4SImode); + + emit_insn (gen_movd_v2hf_to_sse (op1, operands[1])); + + emit_insn (gen_avx512fp16_fix_truncv4si2 (op0, op1)); + + emit_move_insn (operands[0], lowpart_subreg (V2SImode, op0, V4SImode)); + DONE; +}) + +(define_expand "float2" + [(set (match_operand:VHF_32_64 0 "register_operand") + (any_float:VHF_32_64 + (match_operand: 1 "nonimmediate_operand")))] + "TARGET_AVX512FP16 && TARGET_AVX512VL && ix86_partial_vec_fp_math" +{ + rtx op1 = gen_reg_rtx (V8HImode); + rtx op0 = gen_reg_rtx (V8HFmode); + + rtx (*gen_movd_sse) (rtx, rtx) + = gen_mov__to_sse; + emit_insn (gen_movd_sse (op1, operands[1])); + + emit_insn (gen_floatv8hiv8hf2 (op0, op1)); + + emit_move_insn (operands[0], + lowpart_subreg (mode, op0, V8HFmode)); + DONE; +}) + +(define_expand "floatv2siv2hf2" + [(set (match_operand:V2HF 0 "register_operand") + (any_float:V2HF + (match_operand:V2SI 1 "nonimmediate_operand")))] + "TARGET_AVX512FP16 && TARGET_AVX512VL + && TARGET_MMX_WITH_SSE && ix86_partial_vec_fp_math" +{ + rtx op1 = gen_reg_rtx (V4SImode); + rtx op0 = gen_reg_rtx (V8HFmode); + + emit_insn (gen_movq_v2si_to_sse (op1, operands[1])); + + emit_insn (gen_avx512fp16_floatv4siv4hf2 (op0, op1)); + + emit_move_insn (operands[0], lowpart_subreg (V2HFmode, op0, V8HFmode)); + DONE; +}) + +(define_expand "extendv2hfv2sf2" + [(set (match_operand:V2SF 0 "register_operand") + (float_extend:V2SF + (match_operand:V2HF 1 "nonimmediate_operand")))] + "TARGET_AVX512FP16 && TARGET_AVX512VL + && TARGET_MMX_WITH_SSE && ix86_partial_vec_fp_math" +{ + rtx op1 = gen_reg_rtx (V8HFmode); + rtx op0 = gen_reg_rtx (V4SFmode); + + emit_insn (gen_movd_v2hf_to_sse (op1, operands[1])); + + emit_insn (gen_avx512fp16_float_extend_phv4sf2 (op0, op1)); + + emit_move_insn (operands[0], lowpart_subreg (V2SFmode, op0, V4SFmode)); + DONE; +}) + +(define_expand "truncv2sfv2hf2" + [(set (match_operand:V2HF 0 "register_operand") + (float_truncate:V2HF + (match_operand:V2SF 1 "nonimmediate_operand")))] + "TARGET_AVX512FP16 && TARGET_AVX512VL + && TARGET_MMX_WITH_SSE && ix86_partial_vec_fp_math" +{ + rtx op1 = gen_reg_rtx (V4SFmode); + rtx op0 = gen_reg_rtx (V8HFmode); + + emit_insn (gen_movq_v2sf_to_sse (op1, operands[1])); + + emit_insn (gen_avx512fp16_truncv4sfv4hf2 (op0, op1)); + + emit_move_insn (operands[0], lowpart_subreg (V2HFmode, op0, V8HFmode)); + DONE; +}) + ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;; ;; Parallel integral arithmetic diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 9feb63716ef..c988935d4df 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -11019,12 +11019,12 @@ (set_attr "prefix" "maybe_vex") (set_attr "mode" "DF")]) -(define_insn "*vec_concatv8hf_movss" - [(set (match_operand:V8HF 0 "register_operand" "=x,v,v") - (vec_merge:V8HF - (vec_duplicate:V8HF - (match_operand:V2HF 2 "nonimmediate_operand" "x,m,v")) - (match_operand:V8HF 1 "reg_or_0_operand" "0,C,v" ) +(define_insn "*vec_concat_movss" + [(set (match_operand: 0 "register_operand" "=x,v,v") + (vec_merge: + (vec_duplicate: + (match_operand:V2FI_32 2 "nonimmediate_operand" "x,m,v")) + (match_operand: 1 "reg_or_0_operand" "0,C,v" ) (const_int 3)))] "TARGET_SSE" "@ diff --git a/gcc/testsuite/gcc.target/i386/part-vect-hf-convert-1.c b/gcc/testsuite/gcc.target/i386/part-vect-hf-convert-1.c new file mode 100644 index 00000000000..95426015b58 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/part-vect-hf-convert-1.c @@ -0,0 +1,111 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-mavx512fp16 -mavx512vl -O2" } */ +/* { dg-final { scan-assembler-times {(?n)vcvttph2w[ \t]} 2 } } */ +/* { dg-final { scan-assembler-times {(?n)vcvttph2uw[ \t]} 2 } } */ +/* { dg-final { scan-assembler-times {(?n)vcvttph2dq[ \t]} 1 } } */ +/* { dg-final { scan-assembler-times {(?n)vcvttph2udq[ \t]} 1 } } */ +/* { dg-final { scan-assembler-times {(?n)vcvtw2ph[ \t]} 2 } } */ +/* { dg-final { scan-assembler-times {(?n)vcvtuw2ph[ \t]} 2 } } */ +/* { dg-final { scan-assembler-times {(?n)vcvtdq2phx[ \t]} 1 } } */ +/* { dg-final { scan-assembler-times {(?n)vcvtudq2phx[ \t]} 1 } } */ +/* { dg-final { scan-assembler-times {(?n)vcvtph2psx[ \t]} 1 } } */ +/* { dg-final { scan-assembler-times {(?n)vcvtps2phxx[ \t]} 1 } } */ + + +void +fix_32 (short* __restrict pa, _Float16* pb) +{ + for (int i = 0; i != 2; i++) + pa[i] = pb[i]; +} + +void +fix_64 (short* __restrict pa, _Float16* pb) +{ + for (int i = 0; i != 4; i++) + pa[i] = pb[i]; +} + +void +fixuns_32 (unsigned short* __restrict pa, _Float16* pb) +{ + for (int i = 0; i != 2; i++) + pa[i] = pb[i]; +} + +void +fixuns_64 (unsigned short* __restrict pa, _Float16* pb) +{ + for (int i = 0; i != 4; i++) + pa[i] = pb[i]; +} + +void +float_32 (short* __restrict pa, _Float16* pb) +{ + for (int i = 0; i != 2; i++) + pb[i] = pa[i]; +} + +void +float_64 (short* __restrict pa, _Float16* pb) +{ + for (int i = 0; i != 4; i++) + pb[i] = pa[i]; +} + +void +floatuns_32 (unsigned short* __restrict pa, _Float16* pb) +{ + for (int i = 0; i != 2; i++) + pb[i] = pa[i]; +} + +void +floatuns_64 (unsigned short* __restrict pa, _Float16* pb) +{ + for (int i = 0; i != 4; i++) + pb[i] = pa[i]; +} + +void +fix_32si (int* __restrict pa, _Float16* pb) +{ + for (int i = 0; i != 2; i++) + pa[i] = pb[i]; +} + +void +fix_32usi (unsigned int* __restrict pa, _Float16* pb) +{ + for (int i = 0; i != 2; i++) + pa[i] = pb[i]; +} + +void +float_32si (int* __restrict pa, _Float16* pb) +{ + for (int i = 0; i != 2; i++) + pb[i] = pa[i]; +} + +void +float_32usi (unsigned int* __restrict pa, _Float16* pb) +{ + for (int i = 0; i != 2; i++) + pb[i] = pa[i]; +} + +void +float_extend (float* __restrict pa, _Float16* pb) +{ + for (int i = 0; i != 2; i++) + pa[i] = pb[i]; +} + +void +float_truncate (float* __restrict pa, _Float16* pb) +{ + for (int i = 0; i != 2; i++) + pb[i] = pa[i]; +}