From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1666) id 99D0D3857737; Mon, 16 Oct 2023 12:49:15 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 99D0D3857737 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1697460555; bh=1f+kaIeilzFJwGTcs1GQTejJ8/JBw1MOBBCXDfTkIgI=; h=From:To:Subject:Date:From; b=MDSJK2V6yozUefMZrI8BSl00iItMPCG6YU5/RHbJocEn9ir+LF7fI0JcSbe0Pt7D6 FJZ35/8doVzB6/1jVk1Ir1JTeNvS549STyly9hUqyvdpbpAOzxndbYDgTJjN7aXm02 IMfGLN8sRmdDc2uNDolWm/toNabYcwtlyj5KfC/c= Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Richard Biener To: gcc-cvs@gcc.gnu.org Subject: [gcc/rguenth/heads/vect-force-slp] (237 commits) Avoid SLP build failure for unsupported shifts X-Act-Checkin: gcc X-Git-Author: Richard Biener X-Git-Refname: refs/users/rguenth/heads/vect-force-slp X-Git-Oldrev: 2016b3bae4f9aec33052c3e12d9ad4233a62bb6b X-Git-Newrev: 83c9d09888461de024bf83f47469bbb12c8f0d98 Message-Id: <20231016124915.99D0D3857737@sourceware.org> Date: Mon, 16 Oct 2023 12:49:15 +0000 (GMT) List-Id: The branch 'rguenth/heads/vect-force-slp' was updated to point to: 83c9d0988846... Avoid SLP build failure for unsupported shifts It previously pointed to: 2016b3bae4f9... Avoid SLP build failure for unsupported shifts Diff: !!! WARNING: THE FOLLOWING COMMITS ARE NO LONGER ACCESSIBLE (LOST): ------------------------------------------------------------------- 2016b3b... Avoid SLP build failure for unsupported shifts ed3595a... Reduce single-lane SLP testresult noise d281c06... Add FIXME note regarding gcc.dg/vect/pr60276.c runfail with d4d841c... Avoid splitting store dataref groups during SLP discovery 5fb7c61... Properly reject SLP gather with builtin decl 5b531e8... Avoid ICEing with SLP scatter 2caa656... Allow single-lane SLP of not pattern detected gather/scatte d2799c4... Do not account single-lane SLP graphs against discovery lim 8520f38... Allow bigger SLP graphs 8878d6a... Guard SLP optimize latch edge discovery 8e5976f... Handle non-grouped SLP stores 8799d83... Add --param vect-single-lane-slp 634772b... Fail vectorization when not SLP with --param vect-force-slp Summary of changes (added commits): ----------------------------------- 83c9d09... Avoid SLP build failure for unsupported shifts 00c421f... Reduce single-lane SLP testresult noise 5a95558... Add FIXME note regarding gcc.dg/vect/pr60276.c runfail with 2f4a092... Avoid splitting store dataref groups during SLP discovery 4eb4017... Properly reject SLP gather with builtin decl 484ffc3... Avoid ICEing with SLP scatter a01f778... Allow single-lane SLP of not pattern detected gather/scatte 5515521... Do not account single-lane SLP graphs against discovery lim 64a5842... Allow bigger SLP graphs 9552241... Guard SLP optimize latch edge discovery c34b76b... Handle non-grouped SLP stores 3193fdc... Add --param vect-single-lane-slp 8e15af6... Fail vectorization when not SLP with --param vect-force-slp e6d0630... Support 32/64-bit vectorization for conversion between _Flo (*) 96f12b9... Enable vectorization for V2HF/V4HF rounding operations and (*) d5cfabc... Daily bump. (*) 643a522... libgomp.texi: Update "Enabling OpenMP" + OpenACC / invoke.t (*) 67f5d36... libgomp.texi: Improve "OpenACC Environment Variables" (*) 15886c0... libgomp.texi: Use present not future tense (*) ade39f9... sim: add distclean dep for gnulib (*) accccbf... middle-end: Improved RTL expansion of 1LL << x. (*) 5c46cd8... modula2: Add m2.etags rule to gcc/m2/Make-lang.in (*) 3bcc10b... wide-int: Fix estimation of buffer sizes for wide_int print (*) ac90823... d: Merge upstream dmd, druntime f9efc98fd7, phobos a3f22129 (*) 648d307... combine: Fix handling of unsigned constants (*) 77faa3e... RISC-V: Fix vsingle attribute (*) b3cb98d... Daily bump. (*) fd6b17a... libgomp.fortran/allocate-6.f90: Run with -fdump-tree-gimple (*) 578afbc... Fix ICE in set_cell_span, at text-art/table.cc:148 with D f (*) 06d8aee... d: Reduce code duplication of writing generated files. (*) bc238c4... libgomp.texi: Note to 'Memory allocation' sect and missing (*) 969f5c3... Fortran: Support OpenMP's 'allocate' directive for stack va (*) cb01192... middle-end: Allow _BitInt(65535) [PR102989] (*) 78dd49f... RISC-V: Remove redundant iterators. (*) 300d7d3... Daily bump. (*) d78fef5... Fortran: name conflict between internal procedure and deriv (*) 458c253... fortran: fix handling of options -ffpe-trap and -ffpe-summa (*) 8be20f3... Do not add partial equivalences with no uses. (*) 3179ad7... OMP SIMD inbranch call vectorization for AVX512 style masks (*) 63eaccd... Add support for SLP vectorization of OpenMP SIMD clone call (*) 8544efd... RISC-V Regression: Fix FAIL of bb-slp-68.c for RVV (*) 9a82cca... RISC-V: Refine run test cases of math autovec (*) 8c5447a... RISC-V: Add test for FP llfloor auto vectorization (*) 9d67561... RISC-V: Add test for FP ifloor auto vectorization (*) 2943c50... RISC-V: Add test for FP iceil auto vectorization (*) ad0bac8... RISC-V: Add test for FP llceil auto vectorization (*) 24eaada... C99 testsuite readiness: Some verified test case adjustment (*) 0fef2c8... C99 test suite readiness: Some unverified test case adjustm (*) 1c23bfd... C99 test suite readiness: Mark some C89 tests (*) cf611de... or1k: Fix -Wincompatible-pointer-types warning during libgc (*) dab4f3e... arc: Fix -Wincompatible-pointer-types warning during libgcc (*) fbd3923... riscv: Fix -Wincompatible-pointer-types warning during libg (*) 6e5216e... csky: Fix -Wincompatible-pointer-types warning during libgc (*) bdbca40... m68k: Avoid implicit function declaration in libgcc (*) badb798... libstdc++: Fix tr1/8_c_compatibility/cstdio/functions.cc re (*) 6decda1... tree-optimization/111779 - Handle some BIT_FIELD_REFs in SR (*) 35b5bb4... tree-optimization/111773 - avoid CD-DCE of noreturn special (*) 6b58056... RISC-V: Add test for FP llround auto vectorization (*) 2a89656... RISC-V Regression: Fix FAIL of bb-slp-pr69907.c for RVV (*) d53d20a... RISC-V: Add test for FP iroundf auto vectorization (*) 0f40e59... RISC-V: Fix the riscv_legitimize_poly_move issue on targets (*) f0b0507... RISC-V: Leverage stdint-gcc.h for RVV test cases (*) 8f52040... RISC-V: Support FP lfloor/lfloorf auto vectorization (*) ba0cde8... testsuite: Replace many dg-require-thread-fence with dg-req (*) 2a4d9e4... testsuite: Add dg-require-atomic-cmpxchg-word (*) f9ef2e6... Daily bump. (*) 51f7bfa... RISC-V: Support FP lceil/lceilf auto vectorization (*) 611eef7... PR111778, PowerPC: Do not depend on an undefined shift (*) 8bd11fa... libgomp.texi: Clarify OMP_TARGET_OFFLOAD=mandatory (*) f150717... reg-notes.def: Fix up description of REG_NOALIAS (*) d8c3ace... RISC-V: Make xtheadcondmov-indirect tests robust against in (*) 53a9407... wide-int: Fix build with gcc < 12 or clang++ [PR111787] (*) e99ad40... RISCV: Bugfix for incorrect documentation heading nesting (*) de593b3... AArch64: Fix Armv9-a warnings that get emitted whenever a A (*) fb590e4... wide-int: Add simple CHECKING_P stack-protector canary like (*) 0d00385... wide-int: Allow up to 16320 bits wide_int and change widest (*) cd0185b... LibF7: Implement atan2. (*) 2cc4f58... RISC-V: Support FP lround/lroundf auto vectorization (*) dfb4085... dwarf2out: Stop using wide_int in GC structures (*) 05f9831... tree-optimization/111764 - wrong reduction vectorization (*) 5fbd91b... Support Intel USER_MSR (*) 3948844... LoongArch: Modify check_effective_target_vect_int_mod accor (*) a2a51b6... LoongArch: Enable vect.exp for LoongArch. [PR111424] (*) 3c23183... LoongArch: Adjust makefile dependency for loongarch headers (*) 701363d... Fortran: Set hidden string length for pointer components [P (*) 530babc... rs6000: Make 32 bit stack_protect support prefixed insn [PR (*) 610b845... testsuite: Avoid uninit var in pr60510.f [PR111427] (*) f1a05dc... vect: Consider vec_perm costing for VMAT_CONTIGUOUS_REVERSE (*) 0bdb9bb... vect: Get rid of vect_model_store_cost (*) 0a96eed... vect: Adjust vectorizable_store costing on VMAT_CONTIGUOUS_ (*) 6a88202... vect: Adjust vectorizable_store costing on VMAT_LOAD_STORE_ (*) 8b151eb... vect: Adjust vectorizable_store costing on VMAT_ELEMENTWISE (*) 7184d22... vect: Simplify costing on vectorizable_scan_store (*) e00820c... vect: Adjust vectorizable_store costing on VMAT_GATHER_SCAT (*) 3bf2366... vect: Move vect_model_store_cost next to the transform in v (*) 32207b1... vect: Ensure vect store is supported for some VMAT_ELEMENTW (*) e1e127d... x86: set spincount 1 for x86 hybrid platform (*) 6a3302a... RISC-V: Support FP llrint auto vectorization (*) 180b08f... [APX] Support Intel APX PUSH2POP2 (*) d6b7fe1... RISC-V: Support FP irintf auto vectorization (*) 6febf76... Daily bump. (*) 06f36c1... RISC-V: Add TARGET_MIN_VLEN_OPTS to fix the build (*) a3e50ee... RISC-V Adjust long unconditional branch sequence (*) faae30c... RISC-V: Extend riscv_subset_list, preparatory for target at (*) 9452d13... RISC-V: Refactor riscv_option_override and riscv_convert_ve (*) 0363bba... options: Define TARGET__P and TARGET__OPTS_P ma (*) e8d418d... MATCH: [PR111282] Simplify `a & (b ^ ~a)` to `a & b` (*) acfca27... modula2: Narrow subranges to int or unsigned int if ZTYPE i (*) 5ef248c... [PATCH v4 2/2] RISC-V: Add support for XCValu extension in (*) 400efdd... [PATCH v4 1/2] RISC-V: Add support for XCVmac extension in (*) 70b02df... MAINTAINERS: Fix write after approval name order (*) 2b783fe... PR modula2/111675 Incorrect packed record field value passe (*) f6c5e24... RISC-V: Fix incorrect index(offset) of gather/scatter (*) d1e5566... RISC-V: Support FP lrint/lrintf auto vectorization (*) d4de593... RISC-V: Remove XFAIL of ssa-dom-cse-2.c (*) e75bf19... tree-ssa-strlen: optimization skips clobbering store [PR111 (*) c414924... Optimize (ne:SI (subreg:QI (ashift:SI x 7) 0) 0) as (and:SI (*) 23aabde... RISC-V: Enable full coverage vect tests (*) 4efe908... Refine predicate of operands[2] in divv4hf3 with register_o (*) de04f73... RISC-V Regression: Make pattern match more accurate of vect (*) cfe8994... RISC-V Regression: Fix FAIL of vect-multitypes-16.c for RVV (*) 69e3072... Daily bump. (*) 71f9064... RISC-V: far-branch: Handle far jumps and branches for funct (*) bd5719b... c++: mangle multiple levels of template parms [PR109422] (*) 975da6f... MATCH: [PR111679] Add alternative simplification of `a | (( (*) 5bb6a87... RISC-V Regression: Make match patterns more accurate (*) 0b0fcb2... RISC-V Regression: Fix FAIL of predcom-2.c (*) 8a36140... RISC-V Regression: Fix FAIL of pr65947-8.c for RVV (*) ddf17b6... MAINTAINERS: Add myself to write after approval (*) 5255273... RISC-V: Add VLS BOOL mode vcond_mask[PR111751] (*) 70b5c69... tree-optimization/111751 - support 1024 bit vector constant (*) 2f15083... ada: Fix internal error on too large representation clause (*) 42c46cf... ada: Tweak internal subprogram in Ada.Directories (*) 25c253e... ada: Remove superfluous setter procedure (*) e05e5d6... ada: Fix bad finalization of limited aggregate in condition (*) 6bd83c9... ada: Fix infinite loop with multiple limited with clauses (*) 34992e1... ada: Fix filesystem entry filtering (*) f71c631... ada: Tweak documentation comments (*) 85a0ce9... ada: Crash processing pragmas Compile_Time_Error and Compil (*) a704603... RISC-V: Add testcase for SCCVN optimization[PR111751] (*) 7c76c87... Fix missed CSE with a BLKmode entity (*) 4d23049... RISC-V Regression: Fix FAIL of bb-slp-pr65935.c for RVV (*) aaa5a53... arc: Refurbish add.f combiner patterns (*) 4ecb9b0... RISC-V: Add available vector size for RVV (*) fb124f2... Daily bump. (*) cc50337... Fixes for profile count/probability maintenance (*) 08d0f84... analyzer: fix build with gcc < 6 (*) b0892b1... Ensure float equivalences include + and - zero. (*) 5ee5111... Remove unused get_identity_relation. (*) dae2144... RISC-V Regression test: Fix slp-perm-4.c FAIL for RVV (*) e90eddd... RISC-V Regression tests: Fix FAIL of pr97832* for RVV (*) 30b76f8... RISC-V Regression test: Fix FAIL of slp-12a.c (*) db20b83... RISC-V Regression test: Fix FAIL of slp-reduc-4.c for RVV (*) 79e6ea4... RISC-V Regression test: Adapt SLP tests like ARM SVE (*) f849843... RISC-V: Add initial pipeline description for an out-of-orde (*) dee55cf... RISC-V: Support movmisalign of RVV VLA modes (*) 578aa2f... THead: Fix missing CFI directives for th.sdd in prologue. (*) 11b8cf1... tree-optimization/111715 - improve TBAA for access paths wi (*) 841668a... RISC-V: Refine bswap16 auto vectorization code gen (*) 1543f3e... RISC-V Regression test: Fix FAIL of pr45752.c for RVV (*) 3f99b70... testsuite: Fix vect_cond_arith_* dump checks for RVV. (*) 784deda... RISC-V Regression test: Fix FAIL of fast-math-slp-38.c for (*) 34d4168... i386: Implement doubleword right shifts by 1 bit using s[ha (*) 85bd47b... Allow -mno-evex512 usage (*) 43b08ab... Support -mevex512 for AVX512FP16 intrins (*) b549005... Support -mevex512 for AVX512{IFMA,VBMI,VNNI,BF16,VPOPCNTDQ, (*) 8e79b1b... Support -mevex512 for AVX512BW intrins (*) 1b24890... Support -mevex512 for AVX512DQ intrins (*) c1eef66... Support -mevex512 for AVX512F intrins (*) aa9bce3... Disable zmm register and 512 bit libmvec call when !TARGET_ (*) c2a282a... [PATCH 5/5] Add OPTION_MASK_ISA2_EVEX512 for 512 bit builti (*) b74e292... [PATCH 4/5] Add OPTION_MASK_ISA2_EVEX512 for 512 bit builti (*) 031e033... [PATCH 3/5] Add OPTION_MASK_ISA2_EVEX512 for 512 bit builti (*) cb8c718... [PATCH 2/5] Add OPTION_MASK_ISA2_EVEX512 for 512 bit builti (*) 8d4b3b3... [PATCH 1/5] Add OPTION_MASK_ISA2_EVEX512 for 512 bit builti (*) aea8e41... [PATCH 5/5] Push evex512 target for 512 bit intrins (*) 8108b22... [PATCH 4/5] Push evex512 target for 512 bit intrins (*) 03a8504... [PATCH 4/5] Push evex512 target for 512 bit intrins (*) ba8e3f3... [PATCH 2/5] Push evex512 target for 512 bit intrins (*) 79fb476... [PATCH 1/5] Push evex512 target for 512 bit intrins (*) 6882df7... Initial support for -mevex512 (*) 873586e... TEST: Fix dump FAIL for RVV (RISCV-V vector) (*) c1e4747... rs6000: support 32bit inline lrint (*) 5cbe235... rs6000: enable SImode in FP register on P7 (*) 6f28992... s390: Make use of new copysign RTL (*) 86d92c8... [i386] APX EGPR: fix missing patterns that prohibit egpr (*) 00c67d6... Daily bump. (*) 0a0ceb7... libcpp: eliminate LINEMAPS_{ORDINARY,MACRO}_MAPS (*) 45bae18... libcpp: eliminate LINEMAPS_{,ORDINARY_,MACRO_}CACHE (*) a73c80d... libcpp: eliminate LINEMAPS_LAST_ALLOCATED{,_ORDINARY,_MACRO (*) b365e9d... analyzer: improvements to out-of-bounds diagrams [PR111155] (*) 1f68a3e... libcpp: eliminate COMBINE_LOCATION_DATA (*) 25af7c1... libcpp: "const" and other cleanups (*) 94caa6a... diagnostics: fix ICE on sarif output when source file is un (*) b4fc1ab... Support signbit/xorsign/copysign/abs/neg/and/xor/ior/andn f (*) 91fdbd6... Support smin/smax for V2HF/V4HF (*) 6a8edd5... Fortran/OpenMP: Fix handling of strictly structured blocks (*) 3da32cc... rs6000: build constant via li/lis;rldic (*) 8f1a70a... rs6000: build constant via li/lis;rldicl/rldicr (*) 6e5f627... rs6000: build constant via lis;rotldi (*) 25b9175... rs6000: build constant via li;rotldi (*) e067e89... [i386] Fix apx test fails on 32bit target (*) b20e59f... RISC-V: add static-pie support (*) f1ccee6... TEST: Fix XPASS of TSVC testsuites for RVV (*) 752bfdb... RISC-V: Enable more tests of "vect" for RVV (*) df726a7... Daily bump. (*) 3bfde22... aarch64: Enable Cortex-X4 CPU (*) 066a43c... Revert "RISC-V: Add more run test for FP rounding autovec" (*) d77ee4a... [APX EGPR] Handle vex insns that only support GPR16 (5/5) (*) f15b6ee... [APX_EGPR] Handle legacy insns that only support GPR16 (4/5 (*) 1328bb7... [APX EGPR] Handle legacy insns that only support GPR16 (3/5 (*) 797b893... [APX EGPR] Handle legacy insns that only support GPR16 (2/5 (*) e4e8b60... [APX EGPR] Handle legacy insn that only support GPR16 (1/5) (*) f498864... [APX EGPR] Handle GPR16 only vector move insns (*) ccdc0f0... [APX EGPR] Map reg/mem constraints in inline asm to non-EGP (*) 0793ee0... [APX EGPR] Add backend hook for base_reg_class/index_reg_cl (*) 835951d... [APX EGPR] Add register and memory constraints that disallo (*) c9d5040... [APX EGPR] Add 16 new integer general purpose registers (*) e686416... [APX_EGPR] Initial support for APX_F (*) dfa15b4... [APX EGPR] middle-end: Add index_reg_class with insn argume (*) bc4466b... [APX EGPR] middle-end: Add insn argument to base_reg_class (*) 7866984... RISC-V: Add more run test for FP rounding autovec (*) 537d7a4... rs6000: use mtvsrws to move sf from si p9 (*) 5f56b76... rs6000: optimize moving to sf from highpart di (*) a809a55... RISC-V: Bugfix for legitimize address PR/111634 (*) 15c1530... RISC-V: Fix scan-assembler-times of RVV test case (*) 0defa2a... Daily bump. (*) ce658ac... i386: Implement doubleword shift left by 1 bit using add+ad (*) 2551e10... Makefile.tpl: disable -Werror for feedback stage [PR111663] (*) fa8c99c... i386: Split lea into shorter left shift by 2 or 3 bits with (*) c1bc751... RISC-V: const: hide mvconst splitter from IRA (*) 837a12a... Docs: Minimally document standard C/C++ attribute syntax. (*) ddfa439... amdgcn: switch mov insns to compact syntax (*) eb239c7... amdgcn: silence warning (*) e0786ba... libgomp.texi: Document some of the device-memory routines (*) e77428a... MATCH: Fix infinite loop between `vec_cond(vec_cond(a,b,0), (*) 171420f... ipa: Remove ipa_bits (*) (*) This commit already exists in another branch. Because the reference `refs/users/rguenth/heads/vect-force-slp' matches your hooks.email-new-commits-only configuration, no separate email is sent for this commit.