From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1005) id D9AD03858D37; Mon, 16 Oct 2023 22:28:20 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org D9AD03858D37 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1697495300; bh=Lw6TKz5M8FNzWYIZYVBHyfCnycwUgyUkiqVRYZd45Jw=; h=From:To:Subject:Date:From; b=FFFm5f49tUrX5VKbM1zfnqzqpPMzulVGBHI6sS3Q0Oo+yqApCk4TtF6fxqg5//a7H 1xhFGWhpp5Su0D4bRvMfCByVM+WTmHRIXKiZOR5j58F42aUnVt7eQ3tmyzfew3A0CO gmiZ/c5YVHmLmh5vdPKjVqPyue0QFYTUKuUtN0YQ= Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Michael Meissner To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/users/meissner/heads/work139-dmf)] Revert patches X-Act-Checkin: gcc X-Git-Author: Michael Meissner X-Git-Refname: refs/users/meissner/heads/work139-dmf X-Git-Oldrev: 1990e45958f99db0a2f5fcff8c9cc13d7097b974 X-Git-Newrev: c2531704aa39ea32f5a6ad5f6f3e9cf4065eb6bb Message-Id: <20231016222820.D9AD03858D37@sourceware.org> Date: Mon, 16 Oct 2023 22:28:20 +0000 (GMT) List-Id: https://gcc.gnu.org/g:c2531704aa39ea32f5a6ad5f6f3e9cf4065eb6bb commit c2531704aa39ea32f5a6ad5f6f3e9cf4065eb6bb Author: Michael Meissner Date: Mon Oct 16 18:28:17 2023 -0400 Revert patches Diff: --- gcc/config/rs6000/rs6000-c.cc | 2 -- gcc/config/rs6000/rs6000-cpus.def | 6 ---- gcc/config/rs6000/rs6000-opts.h | 4 +-- gcc/config/rs6000/rs6000-tables.opt | 3 -- gcc/config/rs6000/rs6000.cc | 57 +++++++------------------------------ gcc/config/rs6000/rs6000.h | 1 - gcc/config/rs6000/rs6000.md | 2 +- gcc/config/rs6000/rs6000.opt | 4 --- gcc/doc/invoke.texi | 2 +- 9 files changed, 13 insertions(+), 68 deletions(-) diff --git a/gcc/config/rs6000/rs6000-c.cc b/gcc/config/rs6000/rs6000-c.cc index e276c20cccdc..65be0ac43e2e 100644 --- a/gcc/config/rs6000/rs6000-c.cc +++ b/gcc/config/rs6000/rs6000-c.cc @@ -447,8 +447,6 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT flags) rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR9"); if ((flags & OPTION_MASK_POWER10) != 0) rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR10"); - if ((flags & OPTION_MASK_FUTURE) != 0) - rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR_FUTURE"); if ((flags & OPTION_MASK_SOFT_FLOAT) != 0) rs6000_define_or_undefine_macro (define_p, "_SOFT_FLOAT"); if ((flags & OPTION_MASK_RECIP_PRECISION) != 0) diff --git a/gcc/config/rs6000/rs6000-cpus.def b/gcc/config/rs6000/rs6000-cpus.def index a6d9d7bf9a8e..8c530a22da84 100644 --- a/gcc/config/rs6000/rs6000-cpus.def +++ b/gcc/config/rs6000/rs6000-cpus.def @@ -88,10 +88,6 @@ | OPTION_MASK_POWER10 \ | OTHER_POWER10_MASKS) -/* Flags for a potential future processor that may or may not be delivered. */ -#define ISA_FUTURE_MASKS (ISA_3_1_MASKS_SERVER \ - | OPTION_MASK_FUTURE) - /* Flags that need to be turned off if -mno-power9-vector. */ #define OTHER_P9_VECTOR_MASKS (OPTION_MASK_FLOAT128_HW \ | OPTION_MASK_P9_MINMAX) @@ -138,7 +134,6 @@ | OPTION_MASK_FPRND \ | OPTION_MASK_POWER10 \ | OPTION_MASK_P10_FUSION \ - | OPTION_MASK_FUTURE \ | OPTION_MASK_HTM \ | OPTION_MASK_ISEL \ | OPTION_MASK_LOAD_VECTOR_PAIR \ @@ -272,4 +267,3 @@ RS6000_CPU ("powerpc64", PROCESSOR_POWERPC64, OPTION_MASK_PPC_GFXOPT RS6000_CPU ("powerpc64le", PROCESSOR_POWER8, MASK_POWERPC64 | ISA_2_7_MASKS_SERVER | OPTION_MASK_HTM) RS6000_CPU ("rs64", PROCESSOR_RS64A, OPTION_MASK_PPC_GFXOPT | MASK_POWERPC64) -RS6000_CPU ("future", PROCESSOR_FUTURE, MASK_POWERPC64 | ISA_FUTURE_MASKS) diff --git a/gcc/config/rs6000/rs6000-opts.h b/gcc/config/rs6000/rs6000-opts.h index f56f01d6fa59..8040cfdc06eb 100644 --- a/gcc/config/rs6000/rs6000-opts.h +++ b/gcc/config/rs6000/rs6000-opts.h @@ -67,9 +67,7 @@ enum processor_type PROCESSOR_MPCCORE, PROCESSOR_CELL, PROCESSOR_PPCA2, - PROCESSOR_TITAN, - - PROCESSOR_FUTURE + PROCESSOR_TITAN }; diff --git a/gcc/config/rs6000/rs6000-tables.opt b/gcc/config/rs6000/rs6000-tables.opt index 3ff28e39f6c4..b82f8205fa1c 100644 --- a/gcc/config/rs6000/rs6000-tables.opt +++ b/gcc/config/rs6000/rs6000-tables.opt @@ -197,6 +197,3 @@ Enum(rs6000_cpu_opt_value) String(powerpc64le) Value(55) EnumValue Enum(rs6000_cpu_opt_value) String(rs64) Value(56) -EnumValue -Enum(rs6000_cpu_opt_value) String(future) Value(57) - diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc index f8c9ce972a5a..8f06b37171a3 100644 --- a/gcc/config/rs6000/rs6000.cc +++ b/gcc/config/rs6000/rs6000.cc @@ -1800,18 +1800,6 @@ rs6000_cpu_name_lookup (const char *name) return -1; } -/* Look up the index for a specific processor. */ - -static int -rs600_cpu_index_lookup (enum processor_type processor) -{ - for (size_t i = 0; i < ARRAY_SIZE (processor_target_table); i++) - if (processor_target_table[i].processor == processor) - return i; - - return -1; -} - /* Return number of consecutive hard regs needed starting at reg REGNO to hold something of mode MODE. @@ -3758,44 +3746,23 @@ rs6000_option_override_internal (bool global_init_p) rs6000_isa_flags &= ~OPTION_MASK_POWERPC64; #endif - /* At the moment, we don't have explict -mtune=future support. If the user - explicitly tried to use -mtune=future, give a warning. If not, use the - power10 tuning until future tuning is added. */ if (rs6000_tune_index >= 0) - { - enum processor_type cur_proc - = processor_target_table[rs6000_tune_index].processor; - - if (cur_proc == PROCESSOR_FUTURE) - { - static bool future_tune_warning = false; - if (!future_tune_warning) - { - future_tune_warning = true; - warning (0, "%qs is not currently supported", "-mtune=future"); - } - - rs6000_tune_index = rs600_cpu_index_lookup (PROCESSOR_POWER10); - } - tune_index = rs6000_tune_index; - } + tune_index = rs6000_tune_index; else if (cpu_index >= 0) - { - enum processor_type cur_cpu - = processor_target_table[cpu_index].processor; - - rs6000_tune_index = (cur_cpu == PROCESSOR_FUTURE - ? rs600_cpu_index_lookup (PROCESSOR_POWER10) - : cpu_index); - } + rs6000_tune_index = tune_index = cpu_index; else { + size_t i; enum processor_type tune_proc = (TARGET_POWERPC64 ? PROCESSOR_DEFAULT64 : PROCESSOR_DEFAULT); - tune_index = rs600_cpu_index_lookup (tune_proc == PROCESSOR_FUTURE - ? PROCESSOR_POWER10 - : tune_proc); + tune_index = -1; + for (i = 0; i < ARRAY_SIZE (processor_target_table); i++) + if (processor_target_table[i].processor == tune_proc) + { + tune_index = i; + break; + } } if (cpu_index >= 0) @@ -4808,7 +4775,6 @@ rs6000_option_override_internal (bool global_init_p) break; case PROCESSOR_POWER10: - case PROCESSOR_FUTURE: rs6000_cost = &power10_cost; break; @@ -5968,8 +5934,6 @@ rs6000_machine_from_flags (void) /* Disable the flags that should never influence the .machine selection. */ flags &= ~(OPTION_MASK_PPC_GFXOPT | OPTION_MASK_PPC_GPOPT | OPTION_MASK_ISEL); - if ((flags & (ISA_FUTURE_MASKS & ~ISA_3_1_MASKS_SERVER)) != 0) - return "future"; if ((flags & (ISA_3_1_MASKS_SERVER & ~ISA_3_0_MASKS_SERVER)) != 0) return "power10"; if ((flags & (ISA_3_0_MASKS_SERVER & ~ISA_2_7_MASKS_SERVER)) != 0) @@ -24494,7 +24458,6 @@ static struct rs6000_opt_mask const rs6000_opt_masks[] = { "float128-hardware", OPTION_MASK_FLOAT128_HW, false, true }, { "fprnd", OPTION_MASK_FPRND, false, true }, { "power10", OPTION_MASK_POWER10, false, true }, - { "future", OPTION_MASK_FUTURE, false, true }, { "hard-dfp", OPTION_MASK_DFP, false, true }, { "htm", OPTION_MASK_HTM, false, true }, { "isel", OPTION_MASK_ISEL, false, true }, diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h index a9c9a11765cf..22595f6ebd77 100644 --- a/gcc/config/rs6000/rs6000.h +++ b/gcc/config/rs6000/rs6000.h @@ -163,7 +163,6 @@ mcpu=e5500: -me5500; \ mcpu=e6500: -me6500; \ mcpu=titan: -mtitan; \ - mcpu=future: -mfuture; \ !mcpu*: %{mpower9-vector: -mpower9; \ mpower8-vector|mcrypto|mdirect-move|mhtm: -mpower8; \ mvsx: -mpower7; \ diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index bc530948aff2..2a1b5ecfaee2 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -351,7 +351,7 @@ ppc403,ppc405,ppc440,ppc476, ppc8540,ppc8548,ppce300c2,ppce300c3,ppce500mc,ppce500mc64,ppce5500,ppce6500, power4,power5,power6,power7,power8,power9,power10, - rs64a,mpccore,cell,ppca2,titan,future" + rs64a,mpccore,cell,ppca2,titan" (const (symbol_ref "(enum attr_cpu) rs6000_tune"))) ;; The ISA we implement. diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt index 6c8ca106b30b..369095df9eda 100644 --- a/gcc/config/rs6000/rs6000.opt +++ b/gcc/config/rs6000/rs6000.opt @@ -628,10 +628,6 @@ mieee128-constant Target Var(TARGET_IEEE128_CONSTANT) Init(1) Save Generate (do not generate) code that uses the LXVKQ instruction. -mfuture -Target Undocumented Mask(FUTURE) Var(rs6000_isa_flags) -Generate (do not generate) future instructions. - ; Documented parameters -param=rs6000-vect-unroll-limit= diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 3558e7effe78..eb714d18511d 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -29747,7 +29747,7 @@ Supported values for @var{cpu_type} are @samp{401}, @samp{403}, @samp{titan}, @samp{power3}, @samp{power4}, @samp{power5}, @samp{power5+}, @samp{power6}, @samp{power6x}, @samp{power7}, @samp{power8}, @samp{power9}, @samp{power10}, @samp{powerpc}, @samp{powerpc64}, -@samp{powerpc64le}, @samp{rs64}, @samp{future}, and @samp{native}. +@samp{powerpc64le}, @samp{rs64}, and @samp{native}. @option{-mcpu=powerpc}, @option{-mcpu=powerpc64}, and @option{-mcpu=powerpc64le} specify pure 32-bit PowerPC (either