From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 7877) id 9441C3858D33; Tue, 17 Oct 2023 02:09:06 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 9441C3858D33 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1697508546; bh=IKjfEJYEqRGTaXe04VCv4m0KKftR/SOCzDdmNmImqzY=; h=From:To:Subject:Date:From; b=fsFl1hn1gzTSiIBNneFjK01ysWet/owboe9k/Sjvrwqa95i41244DMiYc/trSF6op 9NEUiPxIA+C5EQCxXMCeKRtavTXMelg0V44jF/DwN2ogoXSIToN6WdB9rY+6qgUSAR xDIFEWouZj+g28virIAJ8EhbBJS0Awhy9WCG2njM= MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain; charset="utf-8" From: LuluCheng To: gcc-cvs@gcc.gnu.org Subject: [gcc r14-4675] LoongArch: Fix vec_initv32qiv16qi template to avoid ICE. X-Act-Checkin: gcc X-Git-Author: Chenghui Pan X-Git-Refname: refs/heads/master X-Git-Oldrev: b20c7ee066cb7d952fa193972e8bc6362c6e4063 X-Git-Newrev: 38ad4ad112478167010246848f01ce5e3ecd7c90 Message-Id: <20231017020906.9441C3858D33@sourceware.org> Date: Tue, 17 Oct 2023 02:09:06 +0000 (GMT) List-Id: https://gcc.gnu.org/g:38ad4ad112478167010246848f01ce5e3ecd7c90 commit r14-4675-g38ad4ad112478167010246848f01ce5e3ecd7c90 Author: Chenghui Pan Date: Wed Oct 11 16:41:25 2023 +0800 LoongArch: Fix vec_initv32qiv16qi template to avoid ICE. Following test code triggers unrecognized insn ICE on LoongArch target with "-O3 -mlasx": void foo (unsigned char *dst, unsigned char *src) { for (int y = 0; y < 16; y++) { for (int x = 0; x < 16; x++) dst[x] = src[x] + 1; dst += 32; src += 32; } } ICE info: ./test.c: In function ‘foo’: ./test.c:8:1: error: unrecognizable insn: 8 | } | ^ (insn 15 14 16 4 (set (reg:V32QI 185 [ vect__24.7 ]) (vec_concat:V32QI (reg:V16QI 186) (const_vector:V16QI [ (const_int 0 [0]) repeated x16 ]))) "./test.c":4:19 -1 (nil)) during RTL pass: vregs ./test.c:8:1: internal compiler error: in extract_insn, at recog.cc:2791 0x12028023b _fatal_insn(char const*, rtx_def const*, char const*, int, char const*) /home/panchenghui/upstream/gcc/gcc/rtl-error.cc:108 0x12028026f _fatal_insn_not_found(rtx_def const*, char const*, int, char const*) /home/panchenghui/upstream/gcc/gcc/rtl-error.cc:116 0x120a03c5b extract_insn(rtx_insn*) /home/panchenghui/upstream/gcc/gcc/recog.cc:2791 0x12067ff73 instantiate_virtual_regs_in_insn /home/panchenghui/upstream/gcc/gcc/function.cc:1610 0x12067ff73 instantiate_virtual_regs /home/panchenghui/upstream/gcc/gcc/function.cc:1983 0x12067ff73 execute /home/panchenghui/upstream/gcc/gcc/function.cc:2030 This RTL is generated inside loongarch_expand_vector_group_init function (related to vec_initv32qiv16qi template). Original impl doesn't ensure all vec_concat arguments are register type. This patch adds force_reg() to the vec_concat argument generation. gcc/ChangeLog: * config/loongarch/loongarch.cc (loongarch_expand_vector_group_init): fix impl related to vec_initv32qiv16qi template to avoid ICE. gcc/testsuite/ChangeLog: * gcc.target/loongarch/vector/lasx/lasx-vec-init-1.c: New test. Diff: --- gcc/config/loongarch/loongarch.cc | 3 ++- .../gcc.target/loongarch/vector/lasx/lasx-vec-init-1.c | 14 ++++++++++++++ 2 files changed, 16 insertions(+), 1 deletion(-) diff --git a/gcc/config/loongarch/loongarch.cc b/gcc/config/loongarch/loongarch.cc index 9e1b0d0cfa8a..8fa74393e8e3 100644 --- a/gcc/config/loongarch/loongarch.cc +++ b/gcc/config/loongarch/loongarch.cc @@ -10194,7 +10194,8 @@ loongarch_gen_const_int_vector_shuffle (machine_mode mode, int val) void loongarch_expand_vector_group_init (rtx target, rtx vals) { - rtx ops[2] = { XVECEXP (vals, 0, 0), XVECEXP (vals, 0, 1) }; + rtx ops[2] = { force_reg (E_V16QImode, XVECEXP (vals, 0, 0)), + force_reg (E_V16QImode, XVECEXP (vals, 0, 1)) }; emit_insn (gen_rtx_SET (target, gen_rtx_VEC_CONCAT (E_V32QImode, ops[0], ops[1]))); } diff --git a/gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-vec-init-1.c b/gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-vec-init-1.c new file mode 100644 index 000000000000..28be329822e6 --- /dev/null +++ b/gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-vec-init-1.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-O3" } */ + +void +foo (unsigned char *dst, unsigned char *src) +{ + for (int y = 0; y < 16; y++) + { + for (int x = 0; x < 16; x++) + dst[x] = src[x] + 1; + dst += 32; + src += 32; + } +}