From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1984) id D46D93858428; Wed, 18 Oct 2023 08:54:55 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org D46D93858428 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1697619295; bh=z8lKDFb7417QtjOhuBLqwCMZ2X873j5dP0NRCgivK+8=; h=From:To:Subject:Date:From; b=OrQIKRArUYx2XRk6wNPRy/io7CTwAr0xSS5Q+OTO7umyn0I9OcaYzreqQ9yS2NtF2 0vZ3s9HmiYF1fDFECAKTtvNMNWL1oBDvW+ocCQHG0pAbGajBT/EfZ968sNxueNm/T6 Kkiah0vb5HCiD/WmmwZXH7G8zdoiHdPmYmnQIAzs= MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="utf-8" From: Tamar Christina To: gcc-cvs@gcc.gnu.org Subject: [gcc r14-4715] AArch64: Rewrite simd move immediate patterns to new syntax X-Act-Checkin: gcc X-Git-Author: Tamar Christina X-Git-Refname: refs/heads/master X-Git-Oldrev: b0fe8f2f960d746e61debd61655f231f503bccaa X-Git-Newrev: 04227acbe9e6c60d1e314a6b4f2d949c07f30baa Message-Id: <20231018085455.D46D93858428@sourceware.org> Date: Wed, 18 Oct 2023 08:54:55 +0000 (GMT) List-Id: https://gcc.gnu.org/g:04227acbe9e6c60d1e314a6b4f2d949c07f30baa commit r14-4715-g04227acbe9e6c60d1e314a6b4f2d949c07f30baa Author: Tamar Christina Date: Wed Oct 18 09:34:01 2023 +0100 AArch64: Rewrite simd move immediate patterns to new syntax This rewrites the simd MOV patterns to use the new compact syntax. No change in semantics is expected. This will be needed in follow on patches. This also merges the splits into the define_insn which will also be needed soon. gcc/ChangeLog: PR tree-optimization/109154 * config/aarch64/aarch64-simd.md (*aarch64_simd_mov): Rewrite to new syntax. (*aarch64_simd_mov" - [(set (match_operand:VDMOV 0 "nonimmediate_operand" - "=w, r, m, m, m, w, ?r, ?w, ?r, w, w") - (match_operand:VDMOV 1 "general_operand" - "m, m, Dz, w, r, w, w, r, r, Dn, Dz"))] + [(set (match_operand:VDMOV 0 "nonimmediate_operand") + (match_operand:VDMOV 1 "general_operand"))] "TARGET_FLOAT && (register_operand (operands[0], mode) || aarch64_simd_reg_or_zero (operands[1], mode))" - "@ - ldr\t%d0, %1 - ldr\t%x0, %1 - str\txzr, %0 - str\t%d1, %0 - str\t%x1, %0 - * return TARGET_SIMD ? \"mov\t%0., %1.\" : \"fmov\t%d0, %d1\"; - * return TARGET_SIMD ? \"umov\t%0, %1.d[0]\" : \"fmov\t%x0, %d1\"; - fmov\t%d0, %1 - mov\t%0, %1 - * return aarch64_output_simd_mov_immediate (operands[1], 64); - fmov\t%d0, xzr" - [(set_attr "type" "neon_load1_1reg, load_8, store_8, neon_store1_1reg,\ - store_8, neon_logic, neon_to_gp, f_mcr,\ - mov_reg, neon_move, f_mcr") - (set_attr "arch" "*,*,*,*,*,*,*,*,*,simd,*")] -) - -(define_insn "*aarch64_simd_mov" - [(set (match_operand:VQMOV 0 "nonimmediate_operand" - "=w, Umn, m, w, ?r, ?w, ?r, w, w") - (match_operand:VQMOV 1 "general_operand" - "m, Dz, w, w, w, r, r, Dn, Dz"))] + {@ [cons: =0, 1; attrs: type, arch] + [w , m ; neon_load1_1reg , * ] ldr\t%d0, %1 + [r , m ; load_8 , * ] ldr\t%x0, %1 + [m , Dz; store_8 , * ] str\txzr, %0 + [m , w ; neon_store1_1reg, * ] str\t%d1, %0 + [m , r ; store_8 , * ] str\t%x1, %0 + [w , w ; neon_logic , simd] mov\t%0., %1. + [w , w ; neon_logic , * ] fmov\t%d0, %d1 + [?r, w ; neon_to_gp , simd] umov\t%0, %1.d[0] + [?r, w ; neon_to_gp , * ] fmov\t%x0, %d1 + [?w, r ; f_mcr , * ] fmov\t%d0, %1 + [?r, r ; mov_reg , * ] mov\t%0, %1 + [w , Dn; neon_move , simd] << aarch64_output_simd_mov_immediate (operands[1], 64); + [w , Dz; f_mcr , * ] fmov\t%d0, xzr + } +) + +(define_insn_and_split "*aarch64_simd_mov" + [(set (match_operand:VQMOV 0 "nonimmediate_operand") + (match_operand:VQMOV 1 "general_operand"))] "TARGET_FLOAT && (register_operand (operands[0], mode) || aarch64_simd_reg_or_zero (operands[1], mode))" - "@ - ldr\t%q0, %1 - stp\txzr, xzr, %0 - str\t%q1, %0 - mov\t%0., %1. - # - # - # - * return aarch64_output_simd_mov_immediate (operands[1], 128); - fmov\t%d0, xzr" - [(set_attr "type" "neon_load1_1reg, store_16, neon_store1_1reg,\ - neon_logic, multiple, multiple,\ - multiple, neon_move, fmov") - (set_attr "length" "4,4,4,4,8,8,8,4,4") - (set_attr "arch" "*,*,*,simd,*,*,*,simd,*")] + {@ [cons: =0, 1; attrs: type, arch, length] + [w , m ; neon_load1_1reg , * , 4] ldr\t%q0, %1 + [Umn, Dz; store_16 , * , 4] stp\txzr, xzr, %0 + [m , w ; neon_store1_1reg, * , 4] str\t%q1, %0 + [w , w ; neon_logic , simd, 4] mov\t%0., %1. + [?r , w ; multiple , * , 8] # + [?w , r ; multiple , * , 8] # + [?r , r ; multiple , * , 8] # + [w , Dn; neon_move , simd, 4] << aarch64_output_simd_mov_immediate (operands[1], 128); + [w , Dz; fmov , * , 4] fmov\t%d0, xzr + } + "&& reload_completed + && (REG_P (operands[0]) + && REG_P (operands[1]) + && !(FP_REGNUM_P (REGNO (operands[0])) + && FP_REGNUM_P (REGNO (operands[1]))))" + [(const_int 0)] + { + if (GP_REGNUM_P (REGNO (operands[0])) + && GP_REGNUM_P (REGNO (operands[1]))) + aarch64_simd_emit_reg_reg_move (operands, DImode, 2); + else + aarch64_split_simd_move (operands[0], operands[1]); + DONE; + } ) ;; When storing lane zero we can use the normal STR and its more permissive @@ -276,33 +281,6 @@ [(set_attr "type" "neon_stp_q")] ) - -(define_split - [(set (match_operand:VQMOV 0 "register_operand" "") - (match_operand:VQMOV 1 "register_operand" ""))] - "TARGET_FLOAT - && reload_completed - && GP_REGNUM_P (REGNO (operands[0])) - && GP_REGNUM_P (REGNO (operands[1]))" - [(const_int 0)] -{ - aarch64_simd_emit_reg_reg_move (operands, DImode, 2); - DONE; -}) - -(define_split - [(set (match_operand:VQMOV 0 "register_operand" "") - (match_operand:VQMOV 1 "register_operand" ""))] - "TARGET_FLOAT - && reload_completed - && ((FP_REGNUM_P (REGNO (operands[0])) && GP_REGNUM_P (REGNO (operands[1]))) - || (GP_REGNUM_P (REGNO (operands[0])) && FP_REGNUM_P (REGNO (operands[1]))))" - [(const_int 0)] -{ - aarch64_split_simd_move (operands[0], operands[1]); - DONE; -}) - (define_expand "@aarch64_split_simd_mov" [(set (match_operand:VQMOV 0) (match_operand:VQMOV 1))]