From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 2140) id 06E3D385841B; Thu, 19 Oct 2023 06:00:50 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 06E3D385841B DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1697695250; bh=rzWW934v3Jqekih0RT+v3kVpjPfwz24vq6d5K/rogWU=; h=From:To:Subject:Date:From; b=gv6om0TAWu6D676nt4unoKoa+R57fIOqBk2DTX3ZxrHrSUvYXG/EqYbBzHphopf6u SEuyh8n3frXnjT3ztM3JKJ/zAi4vPlxtLxK1XuTGKOX8qeoor3Q87w2O/nILVb/dj8 CUjg/1+o/1QoSzIO32SpeWnXiqmegQA5eA63GtlU= Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Alexandre Oliva To: gcc-cvs@gcc.gnu.org Subject: [gcc/aoliva/heads/testme] (393 commits) return edge in make_eh_edges X-Act-Checkin: gcc X-Git-Author: Alexandre Oliva X-Git-Refname: refs/users/aoliva/heads/testme X-Git-Oldrev: 3a10b677396864b6227ac77cb2f3720c9637ef4d X-Git-Newrev: 1428a8d4552ac7b28c87eee1b84b90ef13743cc0 Message-Id: <20231019060050.06E3D385841B@sourceware.org> Date: Thu, 19 Oct 2023 06:00:50 +0000 (GMT) List-Id: The branch 'aoliva/heads/testme' was updated to point to: 1428a8d4552a... return edge in make_eh_edges It previously pointed to: 3a10b6773968... enable control flow redundancy hardening unconditionally Diff: !!! WARNING: THE FOLLOWING COMMITS ARE NO LONGER ACCESSIBLE (LOST): ------------------------------------------------------------------- 3a10b67... enable control flow redundancy hardening unconditionally c16b801... hardcfr: check excess visited bits d969d4f... strub: ppc64el internal va-list dbe7ecc... strub: cope with identifier GCing d42e4a1... strub: drop obsolete pp conditionals 1d4e505... set hardcfr eh probs 8d56ede... set strub eh probs 122825e... return edge in make_eh_edges ae69d3f... ppc: testsuite: p9-vec-length: add -mno-strict-align and -m f8196b6... Compile prefix-ds-dq.c with -mno-strict-align bd38fa3... use -mno-strict-align for strlenopt-80.c on powerpc bdc5db1... Introduce strub: machine-independent stack scrubbing 926a6e7... Introduce hardbool attribute for C 5a047dd... hardcfr: fix indirect jump 0b1c956... Control flow redundancy hardening Summary of changes (added commits): ----------------------------------- 1428a8d... return edge in make_eh_edges c66b850... ppc: testsuite: p9-vec-length: add -mno-strict-align and -m ecf1f71... Compile prefix-ds-dq.c with -mno-strict-align a020819... use -mno-strict-align for strlenopt-80.c on powerpc 0308461... Daily bump. (*) b20dbdd... Fix expansion of `(a & 2) != 1` (*) 879c91f... [c] Fix PR 101364: ICE after error due to diagnose_arglist_ (*) 11e6bce... Fix ICE due to c_safe_arg_type_equiv_p not checking for err (*) 3ec8ecb... PR111648: Fix wrong code-gen due to incorrect VEC_PERM_EXPR (*) fe9767e... pru: Implement TARGET_INSN_COST (*) 67f7bf7... LibF7: Implement mul_mant for devices without MUL instructi (*) ff05a3e... aarch64: Replace duplicated selftests (*) bc4bd69... cse: Workaround GCC < 5 bug in cse_insn [PR111852] (*) ef10cb8... diagnostic: add permerror variants with opt (*) af4bb22... OpenMP: Avoid ICE with LTO and 'omp allocate' (*) f1744dd... tree-ssa-math-opts: Fix up match_uaddc_usubc [PR111845] (*) d396176... nvptx: Use fatal_error when -march= is missing not an asser (*) a4184c8... Darwin: Check as for .build_version support and use it if a (*) dd28f90... ifcvt: rewrite args handling to remove lookups (*) 04227ac... AArch64: Rewrite simd move immediate patterns to new syntax (*) b0fe8f2... middle-end: ifcvt: Allow any const IFN in conditional block (*) 4b39aee... middle-end: Fold vec_cond into conditional ternary or binar (*) b588dcb... LoongArch: Use fcmp.caf.s instead of movgr2cf for zeroing a (*) b0372ef... Re-instantiate integer mask to traditional vector mask supp (*) 60c231c... middle-end: maintain LCSSA throughout loop peeling (*) 0c85228... middle-end: updated niters analysis to handle multiple exit (*) d65e38e... middle-end: Refactor vectorizer loop conditionals and separ (*) 46937e1... middle-end: refactor vectorizable_comparison to make the ma (*) c51040c... RISC-V: Optimize consecutive permutation index pattern by v (*) 372c5da... fortran/intrinsic.texi: Add 'intrinsic' to SIGNAL example (*) f019251... Initial Panther Lake Support (*) 2aa97c0... x86: Add m_CORE_HYBRID for hybrid clients tuning (*) 7370c47... Initial Clearwater Forest Support (*) cead92b... Support 32/64-bit vectorization for _Float16 fma related op (*) cf7739d... RISC-V: Enable more tests for dynamic LMUL and bug fix[PR11 (*) fb69acf... Daily bump. (*) 773306e... aarch64: Put LR save slot first in more cases (*) 5758585... aarch64: Use vecs to store register save order (*) aeb3f04... Handle epilogues that contain jumps (*) 5e4abf4... ssa_name_has_boolean_range vs signed-boolean:31 types (*) 1fbb7d7... c++: accepts-invalid with =delete("") [PR111840] (*) 765c3b8... c++: Fix compile-time-hog in cp_fold_immediate_r [PR111660] (*) bac21b7... c++: mangling tweaks (*) 4f87000... c++: Add missing auto_diagnostic_groups to constexpr.cc (*) 9cad427... RISC-V/testsuite/pr111466.c: update test and expected outpu (*) 1f186f6... c: error for function with external and internal linkage [P (*) 5ac63ec... Fortran: out of bounds access with nested implied-do IO [PR (*) 43c2f85... fortran/intrinsic.texi: Improve SIGNAL intrinsic entry (*) b18d1ca... MATCH: [PR111432] Simplify `a & (x | CST)` to a when we kno (*) da65efe... LibF7: Re-generate f7-renames.h to pick up white-space from (*) 305034e... tree-cfg: Add count information when creating new bb in mov (*) ef6696a... PR modula2/111756: Re-building all-gcc after source changes (*) 323209c... tree-optimization/111846 - put simd-clone-info into SLP tre (*) fbdf88a... wide-int-print: Don't print large numbers hexadecimally for (*) 5bb79a4... RISC-V: Fix failed testcase when use -cmodel=medany (*) c4e773b... LibF7: Implement fma / fmal. (*) ce55521... middle-end/111818 - failed DECL_NOT_GIMPLE_REG_P setting of (*) 3aaf704... tree-optimization/111807 - ICE in verify_sra_access_forest (*) 8eb9cdd... expr: don't clear SUBREG_PROMOTED_VAR_P flag for a promoted (*) 38ad4ad... LoongArch: Fix vec_initv32qiv16qi template to avoid ICE. (*) b20c7ee... LoongArch: Delete macro definition ASM_OUTPUT_ALIGN_WITH_NO (*) b25b43c... RISC-V: Fix unexpected big LMUL choosing in dynamic LMUL mo (*) ef8f7e3... d: Forbid taking the address of an intrinsic with no implem (*) e16ace7... Daily bump. (*) b626751... Fix minor problem in stack probing (*) 04013e4... diagnostics: special-case -fdiagnostics-text-art-charset=as (*) f8644b6... diagnostics: fix missing initialization of context->extra_o (*) 1a64156... i386: Allow -mlarge-data-threshold with -mcmodel=large (*) 3287456... RISC-V: NFC: Move scalar block move expansion code into ris (*) c927377... RISC-V/testsuite: add a default march (lacking zfa) to some (*) 04c9cf5... Implement new RTL optimizations pass: fold-mem-offsets (*) 964fd40... d: Merge upstream dmd, druntime 4c18eed967, phobos d945686a (*) c7609ac... MATCH: Improve `A CMP 0 ? A : -A` set of patterns to use bi (*) 29a4453... [PR31531] MATCH: Improve ~a < ~b and ~a < CST, allow a nop (*) 7550130... c++: improve fold-expr location (*) a22eeac... c++: fix truncated diagnostic in C++23 [PR111272] (*) 817a701... ARC: Split asl dst,1,src into bset dst,0,src to implement 1 (*) d6ebe61... s390: Fix expander popcountv8hi2_vx (*) a5fe9f0... RISC-V: Use VLS modes if the NITERS is known and smaller th (*) b7a28c0... use more get_range_query (*) e6d0630... Support 32/64-bit vectorization for conversion between _Flo (*) 96f12b9... Enable vectorization for V2HF/V4HF rounding operations and (*) d5cfabc... Daily bump. (*) 643a522... libgomp.texi: Update "Enabling OpenMP" + OpenACC / invoke.t (*) 67f5d36... libgomp.texi: Improve "OpenACC Environment Variables" (*) 15886c0... libgomp.texi: Use present not future tense (*) ade39f9... sim: add distclean dep for gnulib (*) accccbf... middle-end: Improved RTL expansion of 1LL << x. (*) 5c46cd8... modula2: Add m2.etags rule to gcc/m2/Make-lang.in (*) 3bcc10b... wide-int: Fix estimation of buffer sizes for wide_int print (*) ac90823... d: Merge upstream dmd, druntime f9efc98fd7, phobos a3f22129 (*) 648d307... combine: Fix handling of unsigned constants (*) 77faa3e... RISC-V: Fix vsingle attribute (*) b3cb98d... Daily bump. (*) fd6b17a... libgomp.fortran/allocate-6.f90: Run with -fdump-tree-gimple (*) 578afbc... Fix ICE in set_cell_span, at text-art/table.cc:148 with D f (*) 06d8aee... d: Reduce code duplication of writing generated files. (*) bc238c4... libgomp.texi: Note to 'Memory allocation' sect and missing (*) 969f5c3... Fortran: Support OpenMP's 'allocate' directive for stack va (*) cb01192... middle-end: Allow _BitInt(65535) [PR102989] (*) 78dd49f... RISC-V: Remove redundant iterators. (*) 300d7d3... Daily bump. (*) d78fef5... Fortran: name conflict between internal procedure and deriv (*) 458c253... fortran: fix handling of options -ffpe-trap and -ffpe-summa (*) 8be20f3... Do not add partial equivalences with no uses. (*) 3179ad7... OMP SIMD inbranch call vectorization for AVX512 style masks (*) 63eaccd... Add support for SLP vectorization of OpenMP SIMD clone call (*) 8544efd... RISC-V Regression: Fix FAIL of bb-slp-68.c for RVV (*) 9a82cca... RISC-V: Refine run test cases of math autovec (*) 8c5447a... RISC-V: Add test for FP llfloor auto vectorization (*) 9d67561... RISC-V: Add test for FP ifloor auto vectorization (*) 2943c50... RISC-V: Add test for FP iceil auto vectorization (*) ad0bac8... RISC-V: Add test for FP llceil auto vectorization (*) 24eaada... C99 testsuite readiness: Some verified test case adjustment (*) 0fef2c8... C99 test suite readiness: Some unverified test case adjustm (*) 1c23bfd... C99 test suite readiness: Mark some C89 tests (*) cf611de... or1k: Fix -Wincompatible-pointer-types warning during libgc (*) dab4f3e... arc: Fix -Wincompatible-pointer-types warning during libgcc (*) fbd3923... riscv: Fix -Wincompatible-pointer-types warning during libg (*) 6e5216e... csky: Fix -Wincompatible-pointer-types warning during libgc (*) bdbca40... m68k: Avoid implicit function declaration in libgcc (*) badb798... libstdc++: Fix tr1/8_c_compatibility/cstdio/functions.cc re (*) 6decda1... tree-optimization/111779 - Handle some BIT_FIELD_REFs in SR (*) 35b5bb4... tree-optimization/111773 - avoid CD-DCE of noreturn special (*) 6b58056... RISC-V: Add test for FP llround auto vectorization (*) 2a89656... RISC-V Regression: Fix FAIL of bb-slp-pr69907.c for RVV (*) d53d20a... RISC-V: Add test for FP iroundf auto vectorization (*) 0f40e59... RISC-V: Fix the riscv_legitimize_poly_move issue on targets (*) f0b0507... RISC-V: Leverage stdint-gcc.h for RVV test cases (*) 8f52040... RISC-V: Support FP lfloor/lfloorf auto vectorization (*) ba0cde8... testsuite: Replace many dg-require-thread-fence with dg-req (*) 2a4d9e4... testsuite: Add dg-require-atomic-cmpxchg-word (*) f9ef2e6... Daily bump. (*) 51f7bfa... RISC-V: Support FP lceil/lceilf auto vectorization (*) 611eef7... PR111778, PowerPC: Do not depend on an undefined shift (*) 8bd11fa... libgomp.texi: Clarify OMP_TARGET_OFFLOAD=mandatory (*) f150717... reg-notes.def: Fix up description of REG_NOALIAS (*) d8c3ace... RISC-V: Make xtheadcondmov-indirect tests robust against in (*) 53a9407... wide-int: Fix build with gcc < 12 or clang++ [PR111787] (*) e99ad40... RISCV: Bugfix for incorrect documentation heading nesting (*) de593b3... AArch64: Fix Armv9-a warnings that get emitted whenever a A (*) fb590e4... wide-int: Add simple CHECKING_P stack-protector canary like (*) 0d00385... wide-int: Allow up to 16320 bits wide_int and change widest (*) cd0185b... LibF7: Implement atan2. (*) 2cc4f58... RISC-V: Support FP lround/lroundf auto vectorization (*) dfb4085... dwarf2out: Stop using wide_int in GC structures (*) 05f9831... tree-optimization/111764 - wrong reduction vectorization (*) 5fbd91b... Support Intel USER_MSR (*) 3948844... LoongArch: Modify check_effective_target_vect_int_mod accor (*) a2a51b6... LoongArch: Enable vect.exp for LoongArch. [PR111424] (*) 3c23183... LoongArch: Adjust makefile dependency for loongarch headers (*) 701363d... Fortran: Set hidden string length for pointer components [P (*) 530babc... rs6000: Make 32 bit stack_protect support prefixed insn [PR (*) 610b845... testsuite: Avoid uninit var in pr60510.f [PR111427] (*) f1a05dc... vect: Consider vec_perm costing for VMAT_CONTIGUOUS_REVERSE (*) 0bdb9bb... vect: Get rid of vect_model_store_cost (*) 0a96eed... vect: Adjust vectorizable_store costing on VMAT_CONTIGUOUS_ (*) 6a88202... vect: Adjust vectorizable_store costing on VMAT_LOAD_STORE_ (*) 8b151eb... vect: Adjust vectorizable_store costing on VMAT_ELEMENTWISE (*) 7184d22... vect: Simplify costing on vectorizable_scan_store (*) e00820c... vect: Adjust vectorizable_store costing on VMAT_GATHER_SCAT (*) 3bf2366... vect: Move vect_model_store_cost next to the transform in v (*) 32207b1... vect: Ensure vect store is supported for some VMAT_ELEMENTW (*) e1e127d... x86: set spincount 1 for x86 hybrid platform (*) 6a3302a... RISC-V: Support FP llrint auto vectorization (*) 180b08f... [APX] Support Intel APX PUSH2POP2 (*) d6b7fe1... RISC-V: Support FP irintf auto vectorization (*) 6febf76... Daily bump. (*) 06f36c1... RISC-V: Add TARGET_MIN_VLEN_OPTS to fix the build (*) a3e50ee... RISC-V Adjust long unconditional branch sequence (*) faae30c... RISC-V: Extend riscv_subset_list, preparatory for target at (*) 9452d13... RISC-V: Refactor riscv_option_override and riscv_convert_ve (*) 0363bba... options: Define TARGET__P and TARGET__OPTS_P ma (*) e8d418d... MATCH: [PR111282] Simplify `a & (b ^ ~a)` to `a & b` (*) acfca27... modula2: Narrow subranges to int or unsigned int if ZTYPE i (*) 5ef248c... [PATCH v4 2/2] RISC-V: Add support for XCValu extension in (*) 400efdd... [PATCH v4 1/2] RISC-V: Add support for XCVmac extension in (*) 70b02df... MAINTAINERS: Fix write after approval name order (*) 2b783fe... PR modula2/111675 Incorrect packed record field value passe (*) f6c5e24... RISC-V: Fix incorrect index(offset) of gather/scatter (*) d1e5566... RISC-V: Support FP lrint/lrintf auto vectorization (*) d4de593... RISC-V: Remove XFAIL of ssa-dom-cse-2.c (*) e75bf19... tree-ssa-strlen: optimization skips clobbering store [PR111 (*) c414924... Optimize (ne:SI (subreg:QI (ashift:SI x 7) 0) 0) as (and:SI (*) 23aabde... RISC-V: Enable full coverage vect tests (*) 4efe908... Refine predicate of operands[2] in divv4hf3 with register_o (*) de04f73... RISC-V Regression: Make pattern match more accurate of vect (*) cfe8994... RISC-V Regression: Fix FAIL of vect-multitypes-16.c for RVV (*) 69e3072... Daily bump. (*) 71f9064... RISC-V: far-branch: Handle far jumps and branches for funct (*) bd5719b... c++: mangle multiple levels of template parms [PR109422] (*) 975da6f... MATCH: [PR111679] Add alternative simplification of `a | (( (*) 5bb6a87... RISC-V Regression: Make match patterns more accurate (*) 0b0fcb2... RISC-V Regression: Fix FAIL of predcom-2.c (*) 8a36140... RISC-V Regression: Fix FAIL of pr65947-8.c for RVV (*) ddf17b6... MAINTAINERS: Add myself to write after approval (*) 5255273... RISC-V: Add VLS BOOL mode vcond_mask[PR111751] (*) 70b5c69... tree-optimization/111751 - support 1024 bit vector constant (*) 2f15083... ada: Fix internal error on too large representation clause (*) 42c46cf... ada: Tweak internal subprogram in Ada.Directories (*) 25c253e... ada: Remove superfluous setter procedure (*) e05e5d6... ada: Fix bad finalization of limited aggregate in condition (*) 6bd83c9... ada: Fix infinite loop with multiple limited with clauses (*) 34992e1... ada: Fix filesystem entry filtering (*) f71c631... ada: Tweak documentation comments (*) 85a0ce9... ada: Crash processing pragmas Compile_Time_Error and Compil (*) a704603... RISC-V: Add testcase for SCCVN optimization[PR111751] (*) 7c76c87... Fix missed CSE with a BLKmode entity (*) 4d23049... RISC-V Regression: Fix FAIL of bb-slp-pr65935.c for RVV (*) aaa5a53... arc: Refurbish add.f combiner patterns (*) 4ecb9b0... RISC-V: Add available vector size for RVV (*) fb124f2... Daily bump. (*) cc50337... Fixes for profile count/probability maintenance (*) 08d0f84... analyzer: fix build with gcc < 6 (*) b0892b1... Ensure float equivalences include + and - zero. (*) 5ee5111... Remove unused get_identity_relation. (*) dae2144... RISC-V Regression test: Fix slp-perm-4.c FAIL for RVV (*) e90eddd... RISC-V Regression tests: Fix FAIL of pr97832* for RVV (*) 30b76f8... RISC-V Regression test: Fix FAIL of slp-12a.c (*) db20b83... RISC-V Regression test: Fix FAIL of slp-reduc-4.c for RVV (*) 79e6ea4... RISC-V Regression test: Adapt SLP tests like ARM SVE (*) f849843... RISC-V: Add initial pipeline description for an out-of-orde (*) dee55cf... RISC-V: Support movmisalign of RVV VLA modes (*) 578aa2f... THead: Fix missing CFI directives for th.sdd in prologue. (*) 11b8cf1... tree-optimization/111715 - improve TBAA for access paths wi (*) 841668a... RISC-V: Refine bswap16 auto vectorization code gen (*) 1543f3e... RISC-V Regression test: Fix FAIL of pr45752.c for RVV (*) 3f99b70... testsuite: Fix vect_cond_arith_* dump checks for RVV. (*) 784deda... RISC-V Regression test: Fix FAIL of fast-math-slp-38.c for (*) 34d4168... i386: Implement doubleword right shifts by 1 bit using s[ha (*) 85bd47b... Allow -mno-evex512 usage (*) 43b08ab... Support -mevex512 for AVX512FP16 intrins (*) b549005... Support -mevex512 for AVX512{IFMA,VBMI,VNNI,BF16,VPOPCNTDQ, (*) 8e79b1b... Support -mevex512 for AVX512BW intrins (*) 1b24890... Support -mevex512 for AVX512DQ intrins (*) c1eef66... Support -mevex512 for AVX512F intrins (*) aa9bce3... Disable zmm register and 512 bit libmvec call when !TARGET_ (*) c2a282a... [PATCH 5/5] Add OPTION_MASK_ISA2_EVEX512 for 512 bit builti (*) b74e292... [PATCH 4/5] Add OPTION_MASK_ISA2_EVEX512 for 512 bit builti (*) 031e033... [PATCH 3/5] Add OPTION_MASK_ISA2_EVEX512 for 512 bit builti (*) cb8c718... [PATCH 2/5] Add OPTION_MASK_ISA2_EVEX512 for 512 bit builti (*) 8d4b3b3... [PATCH 1/5] Add OPTION_MASK_ISA2_EVEX512 for 512 bit builti (*) aea8e41... [PATCH 5/5] Push evex512 target for 512 bit intrins (*) 8108b22... [PATCH 4/5] Push evex512 target for 512 bit intrins (*) 03a8504... [PATCH 4/5] Push evex512 target for 512 bit intrins (*) ba8e3f3... [PATCH 2/5] Push evex512 target for 512 bit intrins (*) 79fb476... [PATCH 1/5] Push evex512 target for 512 bit intrins (*) 6882df7... Initial support for -mevex512 (*) 873586e... TEST: Fix dump FAIL for RVV (RISCV-V vector) (*) c1e4747... rs6000: support 32bit inline lrint (*) 5cbe235... rs6000: enable SImode in FP register on P7 (*) 6f28992... s390: Make use of new copysign RTL (*) 86d92c8... [i386] APX EGPR: fix missing patterns that prohibit egpr (*) 00c67d6... Daily bump. (*) 0a0ceb7... libcpp: eliminate LINEMAPS_{ORDINARY,MACRO}_MAPS (*) 45bae18... libcpp: eliminate LINEMAPS_{,ORDINARY_,MACRO_}CACHE (*) a73c80d... libcpp: eliminate LINEMAPS_LAST_ALLOCATED{,_ORDINARY,_MACRO (*) b365e9d... analyzer: improvements to out-of-bounds diagrams [PR111155] (*) 1f68a3e... libcpp: eliminate COMBINE_LOCATION_DATA (*) 25af7c1... libcpp: "const" and other cleanups (*) 94caa6a... diagnostics: fix ICE on sarif output when source file is un (*) b4fc1ab... Support signbit/xorsign/copysign/abs/neg/and/xor/ior/andn f (*) 91fdbd6... Support smin/smax for V2HF/V4HF (*) 6a8edd5... Fortran/OpenMP: Fix handling of strictly structured blocks (*) 3da32cc... rs6000: build constant via li/lis;rldic (*) 8f1a70a... rs6000: build constant via li/lis;rldicl/rldicr (*) 6e5f627... rs6000: build constant via lis;rotldi (*) 25b9175... rs6000: build constant via li;rotldi (*) e067e89... [i386] Fix apx test fails on 32bit target (*) b20e59f... RISC-V: add static-pie support (*) f1ccee6... TEST: Fix XPASS of TSVC testsuites for RVV (*) 752bfdb... RISC-V: Enable more tests of "vect" for RVV (*) df726a7... Daily bump. (*) 3bfde22... aarch64: Enable Cortex-X4 CPU (*) 066a43c... Revert "RISC-V: Add more run test for FP rounding autovec" (*) d77ee4a... [APX EGPR] Handle vex insns that only support GPR16 (5/5) (*) f15b6ee... [APX_EGPR] Handle legacy insns that only support GPR16 (4/5 (*) 1328bb7... [APX EGPR] Handle legacy insns that only support GPR16 (3/5 (*) 797b893... [APX EGPR] Handle legacy insns that only support GPR16 (2/5 (*) e4e8b60... [APX EGPR] Handle legacy insn that only support GPR16 (1/5) (*) f498864... [APX EGPR] Handle GPR16 only vector move insns (*) ccdc0f0... [APX EGPR] Map reg/mem constraints in inline asm to non-EGP (*) 0793ee0... [APX EGPR] Add backend hook for base_reg_class/index_reg_cl (*) 835951d... [APX EGPR] Add register and memory constraints that disallo (*) c9d5040... [APX EGPR] Add 16 new integer general purpose registers (*) e686416... [APX_EGPR] Initial support for APX_F (*) dfa15b4... [APX EGPR] middle-end: Add index_reg_class with insn argume (*) bc4466b... [APX EGPR] middle-end: Add insn argument to base_reg_class (*) 7866984... RISC-V: Add more run test for FP rounding autovec (*) 537d7a4... rs6000: use mtvsrws to move sf from si p9 (*) 5f56b76... rs6000: optimize moving to sf from highpart di (*) a809a55... RISC-V: Bugfix for legitimize address PR/111634 (*) 15c1530... RISC-V: Fix scan-assembler-times of RVV test case (*) 0defa2a... Daily bump. (*) ce658ac... i386: Implement doubleword shift left by 1 bit using add+ad (*) 2551e10... Makefile.tpl: disable -Werror for feedback stage [PR111663] (*) fa8c99c... i386: Split lea into shorter left shift by 2 or 3 bits with (*) c1bc751... RISC-V: const: hide mvconst splitter from IRA (*) 837a12a... Docs: Minimally document standard C/C++ attribute syntax. (*) ddfa439... amdgcn: switch mov insns to compact syntax (*) eb239c7... amdgcn: silence warning (*) e0786ba... libgomp.texi: Document some of the device-memory routines (*) e77428a... MATCH: Fix infinite loop between `vec_cond(vec_cond(a,b,0), (*) 171420f... ipa: Remove ipa_bits (*) 00e167f... RISC-V: Use stdint-gcc.h in rvv testsuite (*) f05b68b... RISC-V: Update comments for FP rounding related autovec (*) 6c44b95... Daily bump. (*) 250dce2... RISC-V: Test memcpy inlined on riscv_v (*) 0ee3266... Delete MALLOC_ABI_ALIGNMENT define from pa32-linux.h (*) 7c0ae1a... libstdc++: [_GLIBCXX_INLINE_VERSION] Add missing symbols (*) 56cbd50... Create a fast VRP pass (*) 3303382... Add a dom based ranger for fast VRP. (*) 480648c... Add outgoing range vector calcualtion API (*) 043a6fc... ipa-utils: avoid uninitialized probabilities on ICF [PR1115 (*) 604e76e... secpol: consistent indentation (*) 2e08795... secpol: add grammatically missing commas / remove one exces (*) c6bff80... i386: Improve memory copy from named address space [PR11165 (*) e866d08... contrib: add mdcompact (*) a28f097... LibF7: Remove uses of attribute pure. (*) c4f05cb... LibF7: Use monic denominator polynomials to save a multipli (*) ebfd27e... sreal: Fix typo in function name (*) 1f7295a... Revert "ipa: Self-DCE of uses of removed call LHSs (PR 1080 (*) 0bda3f2... RISC-V: Remove @ of vec_series (*) 92cf0cf... arc: Update tests predicates when using linux toolchain. (*) 1daa0db... arc: Remove obsolete ccfsm instruction predication mechanis (*) f4d35da... arc: Remove '^' print punct character (*) 728b470... arc: Update/remove ARC specific tests (*) e4b1940... arc: Remove unused/incomplete alignment assembly annotation (*) 6dc4443... Fix SIMD call SLP discovery (*) b583a29... Avoid left around copies when value-numbering BBs (*) ffbd7c3... ipa/111643 - clarify flatten attribute documentation (*) bf2e66e... Daily bump. (*) 4cac1d2... Add a GCC Security policy (*) 4bf77db... libstdc++: Correctly call _string_types function (*) 3ceb109... ARC: Split SImode shifts pre-reload on !TARGET_BARREL_SHIFT (*) f4e7bba... ARC: Correct instruction length attributes. (*) 263369b... PR rtl-optimization/110701: Fix SUBREG SET_DEST handling in (*) d342c9d... libstdc++: _versioned_namespace is always non-None (*) 83ec6e8... libstdc++: Define _versioned_namespace in xmethods.py (*) 027a94c... options: Prevent multidimensional arrays [PR111664] (*) 75e3773... libgomp.texi: Clarify that no other OpenMP context selector (*) 64eb7b0... LoongArch: Replace UNSPEC_FCOPYSIGN with copysign RTL (*) 64eeec2... match.pd: Avoid other build_nonstandard_integer_type calls (*) 7ab0126... match.pd: Fix up a ? cst1 : cst2 regression on signed bool (*) 84284e1... Fortran: Alloc comp of non-finalizable type not finalized [ (*) 96557ee... Daily bump. (*) 1c45319... c++: print source code in print_instantiation_partial_conte (*) 645f2a7... RISC-V: Unescape chars in pr111566.f90 test (*) d8808c3... Don't use range_info_get_range for pointers. (*) 5f18797... contrib/mklog.py: Fix issues reported by flake8 (*) ed8fe3b... ipa-modref: Fix dumping (*) 14d0c50... ipa-sra: Allow IPA-SRA in presence of returns which will be (*) 1be18ea... ipa: Self-DCE of uses of removed call LHSs (PR 108007) (*) 7eb5ce7... Remove pass counting in VRP. (*) ec8e866... Return TRUE only when a global value is updated. (*) c44ca7c... diagnostics: add ctors to text_info; add m_ prefixes to fie (*) 0988121... ARC: Use rlc r0,0 to implement scc_ltu (i.e. carry_flag ? 1 (*) 3ca09d6... aarch64: Convert aarch64 multi choice patterns to new synta (*) 9d31045... recog: Support space in "[ cons" (*) dd1091f... recog: Improve parser for pattern new compact syntax (*) 41d1c9a... Daily bump. (*) 269c259... Add hppa*-*-* to dg-error targets at line 5 (*) c542906... Require target lra in gcc.dg/pr108095.c (*) 8ef36f6... Increase timeout factor for hppa*-*-* in gcc.dg/long_branch (*) 594fe74... contrib: Update Darwin entries in config-list.mk (*) a70b158... Replace UNSPEC_COPYSIGN with copysign RTL (*) 1408202... diagnostics: add diagnostic_output_format class (*) c5c565e... diagnostics: group together source printing fields of diagn (*) c64693f... diagnostics: fix missing init of set_locations_cb (*) 0731889... Arm: Block predication on atomics [PR111235] (*) bada3c2... Revert "ifcvt: replace C++ sort with vec::qsort [PR109154]" (*) f2b23a5... AArch64: Fix scalar xorsign lowering (*) a35ab1c... rtl: relax validate_subreg to allow paradoxical subregs tha (*) 1961058... ifcvt: replace C++ sort with vec::qsort [PR109154] (*) 76547f4... testsuite, Darwin: Skip g++.dg/debug/dwarf2/pr85550.C (*) e465e5e... Fix profiledbootstrap poly_int fallout [PR111642] (*) 9464e72... cpymem for RISC-V with v extension (*) e7a23bb... Daily bump. (*) 5f3da48... Fix typo in add_options_for_riscv_v, add_options_for_riscv_ (*) 86b2ffc... rtl-optimization/110939 Really fix narrow comparison of mem (*) e4a4b8e... RISC-V:Optimize the MASK opt generation (*) f416a3f... Make riscv_vector::legitimize_move adjust SRC in the caller (*) 125781f... Daily bump. (*) 04e772b... RISC-V: Use safe_grow_cleared for vector info [PR111649] (*) 1e68150... gimple-match-head: Fix a pasto in function comment (*) 09b5124... lowerbitint: Fix 2 bitint lowering bugs [PR111625] (*) 9d249b7... vec.h: Uncomment static_assert (*) d6fe757... RISC-V: Add type attribute in *_not_const patt (*) 6cc9904... Remove .PHONY targets when building .fda files during autop (*) 87c0050... Daily bump. (*) c00fcbd... modula2: testsuite correction to m2date.mod (*) 44efc74... Fix INSN costing and more zicond tests (*) 4f1e537... RISC-V: Specify -mabi=lp64d in wredsum_vlmax.c testcase (*) (*) This commit already exists in another branch. Because the reference `refs/users/aoliva/heads/testme' matches your hooks.email-new-commits-only configuration, no separate email is sent for this commit.