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From: Alex Coplan <acoplan@gcc.gnu.org> To: gcc-cvs@gcc.gnu.org Subject: [gcc r14-4742] aarch64, testsuite: Fix up pr71727.c Date: Thu, 19 Oct 2023 10:15:15 +0000 (GMT) [thread overview] Message-ID: <20231019101515.11F743858428@sourceware.org> (raw) https://gcc.gnu.org/g:61ea0a89c6face2ce5651e4819adea5d9b613f3d commit r14-4742-g61ea0a89c6face2ce5651e4819adea5d9b613f3d Author: Alex Coplan <alex.coplan@arm.com> Date: Wed Oct 11 15:57:32 2023 +0000 aarch64, testsuite: Fix up pr71727.c The test is trying to check that we don't use q-register stores with -mstrict-align, so actually check specifically for that. This is a prerequisite to avoid regressing: scan-assembler-not "add\tx0, x0, :" with the upcoming ldp fusion pass, as we change where the ldps are formed such that a register is used rather than a symbolic (lo_sum) address for the first load. gcc/testsuite/ChangeLog: * gcc.target/aarch64/pr71727.c: Adjust scan-assembler-not to make sure we don't have q-register stores with -mstrict-align. Diff: --- gcc/testsuite/gcc.target/aarch64/pr71727.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/gcc/testsuite/gcc.target/aarch64/pr71727.c b/gcc/testsuite/gcc.target/aarch64/pr71727.c index 41fa72bc67e9..226258a76fe9 100644 --- a/gcc/testsuite/gcc.target/aarch64/pr71727.c +++ b/gcc/testsuite/gcc.target/aarch64/pr71727.c @@ -30,4 +30,4 @@ _start (void) } /* { dg-final { scan-assembler-times "mov\tx" 5 {target lp64} } } */ -/* { dg-final { scan-assembler-not "add\tx0, x0, :" {target lp64} } } */ +/* { dg-final { scan-assembler-not {st[rp]\tq[0-9]+} {target lp64} } } */
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