From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1666) id 64E893858D1E; Thu, 19 Oct 2023 13:28:36 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 64E893858D1E DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1697722116; bh=RtQBk95InRFYPHTxGhJAukDuOSZc1Tro8oQy/s6VAdc=; h=From:To:Subject:Date:From; b=CLJp0tn5XTWsS4o/ubEKJvhnHzQ9Fp1dNWjz8uK5TYC7dPA+g/1TCnIytkllgGU22 7QaMfK9VxwiZGg+CGshvt1AvsCtAmHhV0+QOcGAHIp1O4uaQ0ppTVtCosY1E9BSwkv rtBZhE/U7T1znuIadeaJXf55DTx6fws3StQtXHak= Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Richard Biener To: gcc-cvs@gcc.gnu.org Subject: [gcc/rguenth/heads/vect-force-slp] (102 commits) Avoid SLP build failure for unsupported shifts X-Act-Checkin: gcc X-Git-Author: Richard Biener X-Git-Refname: refs/users/rguenth/heads/vect-force-slp X-Git-Oldrev: 83c9d09888461de024bf83f47469bbb12c8f0d98 X-Git-Newrev: 881b485e01e2150757042dfff9640ee813cf31e8 Message-Id: <20231019132836.64E893858D1E@sourceware.org> Date: Thu, 19 Oct 2023 13:28:36 +0000 (GMT) List-Id: The branch 'rguenth/heads/vect-force-slp' was updated to point to: 881b485e01e2... Avoid SLP build failure for unsupported shifts It previously pointed to: 83c9d0988846... Avoid SLP build failure for unsupported shifts Diff: !!! WARNING: THE FOLLOWING COMMITS ARE NO LONGER ACCESSIBLE (LOST): ------------------------------------------------------------------- 83c9d09... Avoid SLP build failure for unsupported shifts 00c421f... Reduce single-lane SLP testresult noise 5a95558... Add FIXME note regarding gcc.dg/vect/pr60276.c runfail with 2f4a092... Avoid splitting store dataref groups during SLP discovery 4eb4017... Properly reject SLP gather with builtin decl 484ffc3... Avoid ICEing with SLP scatter a01f778... Allow single-lane SLP of not pattern detected gather/scatte 5515521... Do not account single-lane SLP graphs against discovery lim 64a5842... Allow bigger SLP graphs 9552241... Guard SLP optimize latch edge discovery c34b76b... Handle non-grouped SLP stores 3193fdc... Add --param vect-single-lane-slp 8e15af6... Fail vectorization when not SLP with --param vect-force-slp Summary of changes (added commits): ----------------------------------- 881b485... Avoid SLP build failure for unsupported shifts d10fc55... Reduce single-lane SLP testresult noise 8469a98... Add FIXME note regarding gcc.dg/vect/pr60276.c runfail with 8b771df... Avoid splitting store dataref groups during SLP discovery ea8175e... Avoid ICEing with SLP scatter b2107f7... Do not account single-lane SLP graphs against discovery lim 46e34ee... Allow bigger SLP graphs b348c0c... Guard SLP optimize latch edge discovery 035bd67... Handle non-grouped SLP stores ae99d20... Add --param vect-single-lane-slp f69b611... Fail vectorization when not SLP with --param vect-force-slp beab5b9... tree-optimization/111131 - SLP for non-IFN gathers (*) b068886... Refactor x86 vectorized gather path (*) 947fb34... aarch64: Generalise TFmode load/store pair patterns (*) 61ea0a8... aarch64, testsuite: Fix up pr71727.c (*) cf776ee... aarch64, testsuite: Tweak sve/pcs/args_9.c to allow stps (*) 583ca5f... aarch64, testsuite: Prevent stp in lr_free_1.c (*) 505f120... rtl-ssa: Support inferring uses of mem in change_insns (*) ba230aa... rtl-ssa: Add entry point to allow re-parenting uses (*) c95aab2... rtl-ssa: Add drop_memory_access helper (*) c338083... rtl-ssa: Fix bug in function_info::add_insn_after (*) faa0e82... x86: Correct ISA enabled for clients since Arrow Lake (*) 56ed105... amdgcn: deprecate Fiji device and multilib (*) 8f4bbdc... LoongArch:Implement the new vector cost model framework. (*) 0881389... LoongArch:Implement vec_widen standard names. (*) a7b7284... LoongArch:Implement avg and sad standard names. (*) 0308461... Daily bump. (*) b20dbdd... Fix expansion of `(a & 2) != 1` (*) 879c91f... [c] Fix PR 101364: ICE after error due to diagnose_arglist_ (*) 11e6bce... Fix ICE due to c_safe_arg_type_equiv_p not checking for err (*) 3ec8ecb... PR111648: Fix wrong code-gen due to incorrect VEC_PERM_EXPR (*) fe9767e... pru: Implement TARGET_INSN_COST (*) 67f7bf7... LibF7: Implement mul_mant for devices without MUL instructi (*) ff05a3e... aarch64: Replace duplicated selftests (*) bc4bd69... cse: Workaround GCC < 5 bug in cse_insn [PR111852] (*) ef10cb8... diagnostic: add permerror variants with opt (*) af4bb22... OpenMP: Avoid ICE with LTO and 'omp allocate' (*) f1744dd... tree-ssa-math-opts: Fix up match_uaddc_usubc [PR111845] (*) d396176... nvptx: Use fatal_error when -march= is missing not an asser (*) a4184c8... Darwin: Check as for .build_version support and use it if a (*) dd28f90... ifcvt: rewrite args handling to remove lookups (*) 04227ac... AArch64: Rewrite simd move immediate patterns to new syntax (*) b0fe8f2... middle-end: ifcvt: Allow any const IFN in conditional block (*) 4b39aee... middle-end: Fold vec_cond into conditional ternary or binar (*) b588dcb... LoongArch: Use fcmp.caf.s instead of movgr2cf for zeroing a (*) b0372ef... Re-instantiate integer mask to traditional vector mask supp (*) 60c231c... middle-end: maintain LCSSA throughout loop peeling (*) 0c85228... middle-end: updated niters analysis to handle multiple exit (*) d65e38e... middle-end: Refactor vectorizer loop conditionals and separ (*) 46937e1... middle-end: refactor vectorizable_comparison to make the ma (*) c51040c... RISC-V: Optimize consecutive permutation index pattern by v (*) 372c5da... fortran/intrinsic.texi: Add 'intrinsic' to SIGNAL example (*) f019251... Initial Panther Lake Support (*) 2aa97c0... x86: Add m_CORE_HYBRID for hybrid clients tuning (*) 7370c47... Initial Clearwater Forest Support (*) cead92b... Support 32/64-bit vectorization for _Float16 fma related op (*) cf7739d... RISC-V: Enable more tests for dynamic LMUL and bug fix[PR11 (*) fb69acf... Daily bump. (*) 773306e... aarch64: Put LR save slot first in more cases (*) 5758585... aarch64: Use vecs to store register save order (*) aeb3f04... Handle epilogues that contain jumps (*) 5e4abf4... ssa_name_has_boolean_range vs signed-boolean:31 types (*) 1fbb7d7... c++: accepts-invalid with =delete("") [PR111840] (*) 765c3b8... c++: Fix compile-time-hog in cp_fold_immediate_r [PR111660] (*) bac21b7... c++: mangling tweaks (*) 4f87000... c++: Add missing auto_diagnostic_groups to constexpr.cc (*) 9cad427... RISC-V/testsuite/pr111466.c: update test and expected outpu (*) 1f186f6... c: error for function with external and internal linkage [P (*) 5ac63ec... Fortran: out of bounds access with nested implied-do IO [PR (*) 43c2f85... fortran/intrinsic.texi: Improve SIGNAL intrinsic entry (*) b18d1ca... MATCH: [PR111432] Simplify `a & (x | CST)` to a when we kno (*) da65efe... LibF7: Re-generate f7-renames.h to pick up white-space from (*) 305034e... tree-cfg: Add count information when creating new bb in mov (*) ef6696a... PR modula2/111756: Re-building all-gcc after source changes (*) 323209c... tree-optimization/111846 - put simd-clone-info into SLP tre (*) fbdf88a... wide-int-print: Don't print large numbers hexadecimally for (*) 5bb79a4... RISC-V: Fix failed testcase when use -cmodel=medany (*) c4e773b... LibF7: Implement fma / fmal. (*) ce55521... middle-end/111818 - failed DECL_NOT_GIMPLE_REG_P setting of (*) 3aaf704... tree-optimization/111807 - ICE in verify_sra_access_forest (*) 8eb9cdd... expr: don't clear SUBREG_PROMOTED_VAR_P flag for a promoted (*) 38ad4ad... LoongArch: Fix vec_initv32qiv16qi template to avoid ICE. (*) b20c7ee... LoongArch: Delete macro definition ASM_OUTPUT_ALIGN_WITH_NO (*) b25b43c... RISC-V: Fix unexpected big LMUL choosing in dynamic LMUL mo (*) ef8f7e3... d: Forbid taking the address of an intrinsic with no implem (*) e16ace7... Daily bump. (*) b626751... Fix minor problem in stack probing (*) 04013e4... diagnostics: special-case -fdiagnostics-text-art-charset=as (*) f8644b6... diagnostics: fix missing initialization of context->extra_o (*) 1a64156... i386: Allow -mlarge-data-threshold with -mcmodel=large (*) 3287456... RISC-V: NFC: Move scalar block move expansion code into ris (*) c927377... RISC-V/testsuite: add a default march (lacking zfa) to some (*) 04c9cf5... Implement new RTL optimizations pass: fold-mem-offsets (*) 964fd40... d: Merge upstream dmd, druntime 4c18eed967, phobos d945686a (*) c7609ac... MATCH: Improve `A CMP 0 ? A : -A` set of patterns to use bi (*) 29a4453... [PR31531] MATCH: Improve ~a < ~b and ~a < CST, allow a nop (*) 7550130... c++: improve fold-expr location (*) a22eeac... c++: fix truncated diagnostic in C++23 [PR111272] (*) 817a701... ARC: Split asl dst,1,src into bset dst,0,src to implement 1 (*) d6ebe61... s390: Fix expander popcountv8hi2_vx (*) a5fe9f0... RISC-V: Use VLS modes if the NITERS is known and smaller th (*) b7a28c0... use more get_range_query (*) (*) This commit already exists in another branch. Because the reference `refs/users/rguenth/heads/vect-force-slp' matches your hooks.email-new-commits-only configuration, no separate email is sent for this commit.