From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 2119) id 1012F3858C2A; Mon, 23 Oct 2023 02:12:37 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 1012F3858C2A DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1698027157; bh=etA5/IRItGKqIFAcN9bC+1TAFQdpP+bltJglG2JQDfM=; h=From:To:Subject:Date:From; b=dgM7PWkb7pyitGZ7gt3IK0iMO+1wpp1VEYJAfgXNgamJDT1NqRFwJsmt7K7B7lYQX ufVFobbgVeZQvlS7diX1ZyeqHjcbm/yZHTE9X0te0VeNBszwdbCc/aF7q1kiWQWSlJ pRJcxzwOE8swZgZlA1jwBYwtH4a7Vp1wYEsxjfyc= Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Jeff Law To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/vendors/riscv/heads/gcc-13-with-riscv-opts)] RISC-V: Prohibit combination of 'E' and 'H' X-Act-Checkin: gcc X-Git-Author: Tsukasa OI X-Git-Refname: refs/vendors/riscv/heads/gcc-13-with-riscv-opts X-Git-Oldrev: 5e72154057f65793a70287486b8968f0916311fe X-Git-Newrev: 17cc344495de08ca322863bede24951e5d01fe42 Message-Id: <20231023021237.1012F3858C2A@sourceware.org> Date: Mon, 23 Oct 2023 02:12:37 +0000 (GMT) List-Id: https://gcc.gnu.org/g:17cc344495de08ca322863bede24951e5d01fe42 commit 17cc344495de08ca322863bede24951e5d01fe42 Author: Tsukasa OI Date: Sat Oct 21 04:28:21 2023 +0000 RISC-V: Prohibit combination of 'E' and 'H' According to the ratified privileged specification (version 20211203), it says: > The hypervisor extension depends on an "I" base integer ISA with 32 x > registers (RV32I or RV64I), not RV32E, which has only 16 x registers. Also in the latest draft, it also prohibits RV64E with the 'H' extension. This commit prohibits the combination of 'E' and 'H' extensions. gcc/ChangeLog: * common/config/riscv/riscv-common.cc (riscv_subset_list::parse): Prohibit 'E' and 'H' combinations. gcc/testsuite/ChangeLog: * gcc.target/riscv/arch-26.c: New test. (cherry picked from commit 11f50716eee812c4a27b66f894e7f3ed0c870534) Diff: --- gcc/common/config/riscv/riscv-common.cc | 4 ++++ gcc/testsuite/gcc.target/riscv/arch-26.c | 4 ++++ 2 files changed, 8 insertions(+) diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc index 860c8521b7b6..526dbb7603be 100644 --- a/gcc/common/config/riscv/riscv-common.cc +++ b/gcc/common/config/riscv/riscv-common.cc @@ -1495,6 +1495,10 @@ riscv_subset_list::parse (const char *arch, location_t loc) error_at (loc, "%<-march=%s%>: z*inx conflicts with floating-point " "extensions", arch); + /* 'H' hypervisor extension requires base ISA with 32 registers. */ + if (subset_list->lookup ("e") && subset_list->lookup ("h")) + error_at (loc, "%<-march=%s%>: h extension requires i extension", arch); + return subset_list; fail: diff --git a/gcc/testsuite/gcc.target/riscv/arch-26.c b/gcc/testsuite/gcc.target/riscv/arch-26.c new file mode 100644 index 000000000000..0b48bc945b58 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/arch-26.c @@ -0,0 +1,4 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32eh -mabi=ilp32e" } */ +int foo() {} +/* { dg-error "'-march=rv32eh': h extension requires i extension" "" { target *-*-* } 0 } */