From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 7924) id 6E62B3858CDA; Mon, 23 Oct 2023 08:00:51 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 6E62B3858CDA DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1698048051; bh=c8k7x6sW3PJYqskshU+Lsm8LZ3ufmATSghCej41400A=; h=From:To:Subject:Date:From; b=tRuXMn+x0Nj1nBIK8PSIxUtGQaGMdobsMoUYtlFSPPSCKueTR5OZCpL6gP5pozHA4 0I7go+opmIPt3ybYcCCzN/aN1jHneKeiTLCVg6oofJCsMnmAgzE9BRTyNrGtADC/x+ in2YVfSEYaHkDy+Ez0R4tb6dh6a7RJxTI6eZ7YiA= MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="utf-8" From: Pan Li To: gcc-cvs@gcc.gnu.org Subject: [gcc r14-4853] RISC-V: Bugfix for merging undef tmp register for trunc X-Act-Checkin: gcc X-Git-Author: Pan Li X-Git-Refname: refs/heads/master X-Git-Oldrev: e1b1cba141aa1c7dadd0d4ac5ff93e3015fdffc0 X-Git-Newrev: 996785db50a4e2df0b0e892cfe39dcf4130fb87d Message-Id: <20231023080051.6E62B3858CDA@sourceware.org> Date: Mon, 23 Oct 2023 08:00:51 +0000 (GMT) List-Id: https://gcc.gnu.org/g:996785db50a4e2df0b0e892cfe39dcf4130fb87d commit r14-4853-g996785db50a4e2df0b0e892cfe39dcf4130fb87d Author: Pan Li Date: Mon Oct 23 15:45:12 2023 +0800 RISC-V: Bugfix for merging undef tmp register for trunc For trunc function autovec, there will be one step like below take MU for the merge operand. rtx tmp = gen_reg_rtx (vec_int_mode); emit_vec_cvt_x_f_rtz (tmp, op_1, mask, vec_fp_mode); The MU will leave the tmp (aka dest register) register unmasked elements unchanged and it is undefined here. This patch would like to adjust the MU to MA. gcc/ChangeLog: * config/riscv/riscv-v.cc (emit_vec_cvt_x_f_rtz): Add insn type arg. (expand_vec_trunc): Take MA instead of MU for cvt_x_f_rtz. Signed-off-by: Pan Li Diff: --- gcc/config/riscv/riscv-v.cc | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc index 91ad6a61fa89..fb6a4e561db4 100644 --- a/gcc/config/riscv/riscv-v.cc +++ b/gcc/config/riscv/riscv-v.cc @@ -4144,12 +4144,20 @@ emit_vec_cvt_f_x (rtx op_dest, rtx op_src, rtx mask, static void emit_vec_cvt_x_f_rtz (rtx op_dest, rtx op_src, rtx mask, - machine_mode vec_mode) + insn_type type, machine_mode vec_mode) { - rtx cvt_x_ops[] = {op_dest, mask, op_dest, op_src}; insn_code icode = code_for_pred (FIX, vec_mode); - emit_vlmax_insn (icode, UNARY_OP_TAMU, cvt_x_ops); + if (type & USE_VUNDEF_MERGE_P) + { + rtx cvt_x_ops[] = {op_dest, mask, op_src}; + emit_vlmax_insn (icode, type, cvt_x_ops); + } + else + { + rtx cvt_x_ops[] = {op_dest, mask, op_dest, op_src}; + emit_vlmax_insn (icode, type, cvt_x_ops); + } } void @@ -4285,7 +4293,7 @@ expand_vec_trunc (rtx op_0, rtx op_1, machine_mode vec_fp_mode, /* Step-3: Convert to integer on mask, rounding to zero (aka truncate). */ rtx tmp = gen_reg_rtx (vec_int_mode); - emit_vec_cvt_x_f_rtz (tmp, op_1, mask, vec_fp_mode); + emit_vec_cvt_x_f_rtz (tmp, op_1, mask, UNARY_OP_TAMA, vec_fp_mode); /* Step-4: Convert to floating-point on mask for the rint result. */ emit_vec_cvt_f_x (op_0, tmp, mask, UNARY_OP_TAMU_FRM_DYN, vec_fp_mode);