From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 7924) id 98BF33858C2D; Mon, 23 Oct 2023 09:58:16 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 98BF33858C2D DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1698055096; bh=5du3CPLsdVqG3gyfBEMZL+9jjEPniwaNNef80h+Auk4=; h=From:To:Subject:Date:From; b=DiQJ8yZs+5O0CragdlmwHHtoIfOXPMd9ZAEuuHDt9BLWmv9CVNDX1+pnH7c8ZgNmC UAfBPh5fm+wSv4ofEif+ygb6W88j6eH94og4aStUSLNtACuVmKF0ZC1/CahVU8YZ3u 6AlzLvvIf5HOvPWOzqSkS7KNC2GDpibBs9yeAI7E= MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="utf-8" From: Pan Li To: gcc-cvs@gcc.gnu.org Subject: [gcc r14-4855] RISC-V: Remove unnecessary asm check for vec cvt X-Act-Checkin: gcc X-Git-Author: Pan Li X-Git-Refname: refs/heads/master X-Git-Oldrev: 0093821426cc22dbe40d46eb763dfc9cf58f8cb1 X-Git-Newrev: 09c9de06074ced7a4beb148bcf9611a5c5fb0d61 Message-Id: <20231023095816.98BF33858C2D@sourceware.org> Date: Mon, 23 Oct 2023 09:58:16 +0000 (GMT) List-Id: https://gcc.gnu.org/g:09c9de06074ced7a4beb148bcf9611a5c5fb0d61 commit r14-4855-g09c9de06074ced7a4beb148bcf9611a5c5fb0d61 Author: Pan Li Date: Mon Oct 23 17:53:20 2023 +0800 RISC-V: Remove unnecessary asm check for vec cvt The vsetvl asm check is unnecessary for the vector convert. We should be focus for constrait and leave the vsetvl test to the vsetvl pass. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/unop/cvt-0.c: Remove the vsetvl asm check from func body. * gcc.target/riscv/rvv/autovec/unop/cvt-1.c: Ditto. Signed-off-by: Pan Li Diff: --- gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/cvt-0.c | 3 +-- gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/cvt-1.c | 3 +-- 2 files changed, 2 insertions(+), 4 deletions(-) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/cvt-0.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/cvt-0.c index 762b14089943..7d66ed3e9435 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/cvt-0.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/cvt-0.c @@ -7,9 +7,8 @@ /* ** test_int65_to_fp16: ** ... -** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*mf2,\s*ta,\s*ma ** vfncvt\.f\.x\.w\s+v[0-9]+,\s*v[0-9]+ -** vsetvli\s+zero,\s*zero,\s*e16,\s*mf4,\s*ta,\s*ma +** ... ** vfncvt\.f\.f\.w\s+v[0-9]+,\s*v[0-9]+ ** ... */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/cvt-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/cvt-1.c index 3180ba3612c7..af08c51ef8b3 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/cvt-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/cvt-1.c @@ -7,9 +7,8 @@ /* ** test_uint65_to_fp16: ** ... -** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*mf2,\s*ta,\s*ma ** vfncvt\.f\.xu\.w\s+v[0-9]+,\s*v[0-9]+ -** vsetvli\s+zero,\s*zero,\s*e16,\s*mf4,\s*ta,\s*ma +** ... ** vfncvt\.f\.f\.w\s+v[0-9]+,\s*v[0-9]+ ** ... */