From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 7930) id A14E43858D37; Tue, 24 Oct 2023 07:48:18 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org A14E43858D37 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1698133698; bh=ADghpKduS1IIchm/WSh4QBOP51TKh4sZax6rg3CrkFk=; h=From:To:Subject:Date:From; b=aF/QmiuHNiznG+dEexubwi8bCaWjZcnqYdJP5G/gNOM7gYC8sD7n3cpc54aoPHQQ7 m2nuJgj7N3XQ2iRxWn0BtrZ0bLSP9HcA2JWl92197qvj6bCHJYrqWjhl0W2ZyolNtn qJK6K00SHCQ0I6vMWzwlt6cvdA9umyfH+rKvV6cE= MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="utf-8" From: Li Xu To: gcc-cvs@gcc.gnu.org Subject: [gcc r14-4879] RISC-V: Fix ICE of RVV vget/vset intrinsic[PR111935] X-Act-Checkin: gcc X-Git-Author: xuli X-Git-Refname: refs/heads/master X-Git-Oldrev: eaf75155f38a51b2d9d49c6c1b1e1639e3d0591a X-Git-Newrev: b44d4ff7b43ff6a34d5c074c7ade03c4a38974fa Message-Id: <20231024074818.A14E43858D37@sourceware.org> Date: Tue, 24 Oct 2023 07:48:18 +0000 (GMT) List-Id: https://gcc.gnu.org/g:b44d4ff7b43ff6a34d5c074c7ade03c4a38974fa commit r14-4879-gb44d4ff7b43ff6a34d5c074c7ade03c4a38974fa Author: xuli Date: Tue Oct 24 07:39:02 2023 +0000 RISC-V: Fix ICE of RVV vget/vset intrinsic[PR111935] Calling vget/vset intrinsic without receiving a return value will cause a crash. Because in this case e.target is null. This patch should be backported to releases/gcc-13. PR target/111935 gcc/ChangeLog: * config/riscv/riscv-vector-builtins-bases.cc: fix bug. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/pr111935.c: New test. Diff: --- gcc/config/riscv/riscv-vector-builtins-bases.cc | 4 ++++ gcc/testsuite/gcc.target/riscv/rvv/base/pr111935.c | 26 ++++++++++++++++++++++ 2 files changed, 30 insertions(+) diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc b/gcc/config/riscv/riscv-vector-builtins-bases.cc index ab12e1309079..0b1409a52e07 100644 --- a/gcc/config/riscv/riscv-vector-builtins-bases.cc +++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc @@ -1740,6 +1740,8 @@ public: rtx expand (function_expander &e) const override { + if (!e.target) + return NULL_RTX; rtx dest = expand_normal (CALL_EXPR_ARG (e.exp, 0)); gcc_assert (riscv_v_ext_vector_mode_p (GET_MODE (dest))); rtx index = expand_normal (CALL_EXPR_ARG (e.exp, 1)); @@ -1777,6 +1779,8 @@ public: rtx expand (function_expander &e) const override { + if (!e.target) + return NULL_RTX; rtx src = expand_normal (CALL_EXPR_ARG (e.exp, 0)); gcc_assert (riscv_v_ext_vector_mode_p (GET_MODE (src))); rtx index = expand_normal (CALL_EXPR_ARG (e.exp, 1)); diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111935.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111935.c new file mode 100644 index 000000000000..0b936d849a17 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111935.c @@ -0,0 +1,26 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O0 -Wno-psabi" } */ + +#include "riscv_vector.h" + +inline vuint32m4_t __attribute__((__always_inline__)) transpose_indexes() { + static const uint32_t idx_[16] = {0, 4, 8, 12, + 1, 5, 9, 13, + 2, 6, 10, 14, + 3, 7, 11, 15}; + return __riscv_vle32_v_u32m4(idx_, 16); +} + +void pffft_real_preprocess_4x4(const float *in) { + vfloat32m1_t r0=__riscv_vle32_v_f32m1(in,4); + vfloat32m4_t tmp = __riscv_vundefined_f32m4(); + tmp = __riscv_vset_v_f32m1_f32m4(tmp, 0, r0); + tmp = __riscv_vset_v_f32m1_f32m4(tmp, 1, r0); + tmp = __riscv_vset_v_f32m1_f32m4(tmp, 2, r0); + tmp = __riscv_vset_v_f32m1_f32m4(tmp, 3, r0); + tmp = __riscv_vrgather_vv_f32m4(tmp, transpose_indexes(), 16); + r0 = __riscv_vget_v_f32m4_f32m1(tmp, 0); +} + +/* { dg-final { scan-assembler-times {vl[0-9]+re[0-9]+\.v\s+v[0-9]+,\s*0\([a-z]+[0-9]+\)} 10 } } */ +/* { dg-final { scan-assembler-times {vs[0-9]+r\.v\s+v[0-9]+,\s*0\([a-z]+[0-9]+\)} 8 } } */