[gcc(refs/vendors/riscv/heads/ext-dce)] Added pr111384.c and riscv/mem-extend.c tests

[gcc(refs/vendors/riscv/heads/ext-dce)] Added pr111384.c and riscv/mem-extend.c tests

[Jivan Hakobyan]

https://gcc.gnu.org/g:8ee8193675df834fb5f7c7555531934bbb1ec6b5

commit 8ee8193675df834fb5f7c7555531934bbb1ec6b5
Author: Jivan Hakobyan <jivanhakobyan9@gmail.com>
Date:   Tue Nov 14 19:31:39 2023 +0400

    Added pr111384.c and riscv/mem-extend.c tests

Diff:
---
 gcc/testsuite/gcc.dg/pr111384.c             | 11 +++++++++++
 gcc/testsuite/gcc.target/riscv/mem-extend.c | 13 +++++++++++++
 2 files changed, 24 insertions(+)

diff --git a/gcc/testsuite/gcc.dg/pr111384.c b/gcc/testsuite/gcc.dg/pr111384.c
new file mode 100644
index 00000000000..a4e77d4aeb6
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/pr111384.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-options "-O1 -fdump-rtl-ext_dce" } */
+/* { dg-final { scan-rtl-dump {Successfully transformed} "ext_dce" } } */
+
+void
+foo(unsigned int src, unsigned short *dst1, unsigned short *dst2)
+{
+    *dst1 = src;
+    *dst2 = src;
+}
+
diff --git a/gcc/testsuite/gcc.target/riscv/mem-extend.c b/gcc/testsuite/gcc.target/riscv/mem-extend.c
new file mode 100644
index 00000000000..c67f12dfc35
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/mem-extend.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zbb" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+void
+foo(short *d, short *tmp) {
+    int x = d[0] + d[1];
+    int y = d[2] + d[3];
+    tmp[0] = x + y;
+    tmp[1] = x - y;
+}
+
+/* { dg-final { scan-assembler-not {\mzext\.h\M} } } */