[gcc r14-5453] Fix ICE generating uniform vector masks

[gcc r14-5453] Fix ICE generating uniform vector masks

[Andrew Stubbs]

https://gcc.gnu.org/g:948b8b6e0e50958ecf56d4d9fb7ac16f245d9cc3

commit r14-5453-g948b8b6e0e50958ecf56d4d9fb7ac16f245d9cc3
Author: Andrew Stubbs <ams@codesourcery.com>
Date:   Tue Nov 14 16:07:37 2023 +0000

    Fix ICE generating uniform vector masks
    
    Most targets have an "and" instructions for their vector mask size, but RISC-V
    only has DImode "and".  Fixed by allowing wider instruction modes.
    
    gcc/ChangeLog:
    
            PR target/112481
            * expr.cc (store_constructor): Use OPTAB_WIDEN for mask adjustment.

Diff:
---
 gcc/expr.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/expr.cc b/gcc/expr.cc
index 3e2a678710d..556bcf7ef59 100644
--- a/gcc/expr.cc
+++ b/gcc/expr.cc
@@ -7489,7 +7489,7 @@ store_constructor (tree exp, rtx target, int cleared, poly_int64 size,
 	    if (maybe_ne (GET_MODE_PRECISION (mode), nunits))
 	      tmp = expand_binop (mode, and_optab, tmp,
 				  GEN_INT ((1 << nunits) - 1), target,
-				  true, OPTAB_DIRECT);
+				  true, OPTAB_WIDEN);
 	    if (tmp != target)
 	      emit_move_insn (target, tmp);
 	    break;