From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 7924) id 16F773858CD1; Wed, 15 Nov 2023 07:41:08 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 16F773858CD1 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1700034068; bh=35lTdrk67eXywHadUUvwyeMJtvGqCI8AN/CpunX7rKY=; h=From:To:Subject:Date:From; b=fKQ6ZFInFHqDJH9dUiUJHQ4L298GCrUQe9fnuVSNIijV5uX4LQcn3kaGUPY4jjAJc e9XV4+iiuA9cKY5eAxJy2b15nZNcViNiWPW/EFgmGZc0IOlGAnQ0L5OE3dV584xj5n YctQ7UecuG7K+M/rdU7LzsfeKjr1MCPHiApQ4khE= MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="utf-8" From: Pan Li To: gcc-cvs@gcc.gnu.org Subject: [gcc r14-5479] RISC-V: Disallow RVV mode address for any load/store[PR112535] X-Act-Checkin: gcc X-Git-Author: Juzhe-Zhong X-Git-Refname: refs/heads/master X-Git-Oldrev: 5f580e24088b85be95aeae0ceb2edff0cea861dd X-Git-Newrev: d85161a73b9bdd382e62ca1ba3f9f962971a9695 Message-Id: <20231115074108.16F773858CD1@sourceware.org> Date: Wed, 15 Nov 2023 07:41:08 +0000 (GMT) List-Id: https://gcc.gnu.org/g:d85161a73b9bdd382e62ca1ba3f9f962971a9695 commit r14-5479-gd85161a73b9bdd382e62ca1ba3f9f962971a9695 Author: Juzhe-Zhong Date: Wed Nov 15 15:15:08 2023 +0800 RISC-V: Disallow RVV mode address for any load/store[PR112535] This patch is quite obvious patch which disallow for load/store address register with RVV mode. PR target/112535 gcc/ChangeLog: * config/riscv/riscv.cc (riscv_legitimate_address_p): Disallow RVV modes base address. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/pr112535.c: New test. Diff: --- gcc/config/riscv/riscv.cc | 4 ++++ gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112535.c | 17 +++++++++++++++++ 2 files changed, 21 insertions(+) diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index ecee7eb4727..e919850fc6c 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -1427,6 +1427,10 @@ static bool riscv_legitimate_address_p (machine_mode mode, rtx x, bool strict_p, code_helper = ERROR_MARK) { + /* Disallow RVV modes base address. + E.g. (mem:SI (subreg:DI (reg:V1DI 155) 0). */ + if (SUBREG_P (x) && riscv_v_ext_mode_p (GET_MODE (SUBREG_REG (x)))) + return false; struct riscv_address_info addr; return riscv_classify_address (&addr, x, mode, strict_p); diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112535.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112535.c new file mode 100644 index 00000000000..95799aab8d2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112535.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */ + +int *a, *f; +char b, c; +int ***d; +static int ****e = &d; +void g() { + c = 3; + for (; c; c--) + if (c < 8) { + f = 0; + ***e = a; + } + if (b) + ***d = 0; +}