From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1984) id C7DD73858C39; Wed, 15 Nov 2023 14:56:18 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org C7DD73858C39 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1700060178; bh=w6pdB4VVh26Pvz0DeCJjkZloQR0rZvSbNvj5aIvMisI=; h=From:To:Subject:Date:From; b=CN9pMubCchNIB6UM2ngrIFB3syFS1nRknyh0NDIdkXQJwex7XJH7+pIMDyOqtiB/C j6b4utY8IiroVm8bQBuvyt+zGFPad5Qnm1sUK5ZzQgyPVah5FfYt+XIGm9XIiQJaOB E3a+UvYk7qZLpIJrdYk8GhQ+Dmz++Gp3BGV1cZeY= Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Tamar Christina To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/users/tnfchris/heads/gcc-14-early-break)] arm: Add MVE cbranch implementation X-Act-Checkin: gcc X-Git-Author: Tamar Christina X-Git-Refname: refs/users/tnfchris/heads/gcc-14-early-break X-Git-Oldrev: c0ce98ac92488b94ab6b998b98f8ae652496318d X-Git-Newrev: b7f6c1783838e81a78a3a2e503c132b9dfd0926a Message-Id: <20231115145618.C7DD73858C39@sourceware.org> Date: Wed, 15 Nov 2023 14:56:18 +0000 (GMT) List-Id: https://gcc.gnu.org/g:b7f6c1783838e81a78a3a2e503c132b9dfd0926a commit b7f6c1783838e81a78a3a2e503c132b9dfd0926a Author: Tamar Christina Date: Fri Jun 23 18:20:45 2023 +0100 arm: Add MVE cbranch implementation Reviewed at https://reviewboard.gnu.aws.arm.com/r/17981/ Diff: --- gcc/config/arm/arm.cc | 9 ++ gcc/config/arm/mve.md | 15 +++ .../gcc.target/arm/mve/vect-early-break-cbranch.c | 117 +++++++++++++++++++++ gcc/testsuite/lib/target-supports.exp | 2 + 4 files changed, 143 insertions(+) diff --git a/gcc/config/arm/arm.cc b/gcc/config/arm/arm.cc index 620ef7bfb2f..73b340027ae 100644 --- a/gcc/config/arm/arm.cc +++ b/gcc/config/arm/arm.cc @@ -11883,6 +11883,15 @@ arm_rtx_costs_internal (rtx x, enum rtx_code code, enum rtx_code outer_code, || TARGET_HAVE_MVE) && simd_immediate_valid_for_move (x, mode, NULL, NULL)) *cost = COSTS_N_INSNS (1); + else if (TARGET_HAVE_MVE + && outer_code == COMPARE + && VALID_MVE_PRED_MODE (mode)) + /* MVE allows very limited instructions on VPT.P0, however comparisons + to 0 do not require us to materialze this constant or require a + predicate comparison as we can go through SImode. For that reason + allow P0 CMP 0 as a cheap operation such that the 0 isn't forced to + registers as we can't compare two predicates. */ + *cost = COSTS_N_INSNS (1); else *cost = COSTS_N_INSNS (4); return true; diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md index 366cec0812a..fa2ca05fe8f 100644 --- a/gcc/config/arm/mve.md +++ b/gcc/config/arm/mve.md @@ -6603,6 +6603,21 @@ DONE; }) +(define_expand "cbranch4" + [(set (pc) (if_then_else + (match_operator 0 "expandable_comparison_operator" + [(match_operand:MVE_7 1 "register_operand") + (match_operand:MVE_7 2 "zero_operand")]) + (label_ref (match_operand 3 "" "")) + (pc)))] + "TARGET_HAVE_MVE" +{ + rtx val = gen_reg_rtx (SImode); + emit_move_insn (val, gen_lowpart (SImode, operands[1])); + emit_jump_insn (gen_cbranchsi4 (operands[0], val, const0_rtx, operands[3])); + DONE; +}) + ;; Reinterpret operand 1 in operand 0's mode, without changing its contents. (define_expand "@arm_mve_reinterpret" [(set (match_operand:MVE_vecs 0 "register_operand") diff --git a/gcc/testsuite/gcc.target/arm/mve/vect-early-break-cbranch.c b/gcc/testsuite/gcc.target/arm/mve/vect-early-break-cbranch.c new file mode 100644 index 00000000000..c3b8506dca0 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/vect-early-break-cbranch.c @@ -0,0 +1,117 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-options "-O3" } */ +/* { dg-final { check-function-bodies "**" "" "" } } */ + +#define N 640 +int a[N] = {0}; +int b[N] = {0}; + +/* +** f1: +** ... +** vcmp.s32 gt, q[0-9]+, q[0-9]+ +** vmrs r[0-9]+, p0 @ movhi +** cbnz r[0-9]+, \.L[0-9]+ +** ... +*/ +void f1 () +{ + for (int i = 0; i < N; i++) + { + b[i] += a[i]; + if (a[i] > 0) + break; + } +} + +/* +** f2: +** ... +** vcmp.s32 ge, q[0-9]+, q[0-9]+ +** vmrs r[0-9]+, p0 @ movhi +** cbnz r[0-9]+, \.L[0-9]+ +** ... +*/ +void f2 () +{ + for (int i = 0; i < N; i++) + { + b[i] += a[i]; + if (a[i] >= 0) + break; + } +} + +/* +** f3: +** ... +** vcmp.i32 eq, q[0-9]+, q[0-9]+ +** vmrs r[0-9]+, p0 @ movhi +** cbnz r[0-9]+, \.L[0-9]+ +** ... +*/ +void f3 () +{ + for (int i = 0; i < N; i++) + { + b[i] += a[i]; + if (a[i] == 0) + break; + } +} + +/* +** f4: +** ... +** vcmp.i32 ne, q[0-9]+, q[0-9]+ +** vmrs r[0-9]+, p0 @ movhi +** cbnz r[0-9]+, \.L[0-9]+ +** ... +*/ +void f4 () +{ + for (int i = 0; i < N; i++) + { + b[i] += a[i]; + if (a[i] != 0) + break; + } +} + +/* +** f5: +** ... +** vcmp.s32 lt, q[0-9]+, q[0-9]+ +** vmrs r[0-9]+, p0 @ movhi +** cbnz r[0-9]+, \.L[0-9]+ +** ... +*/ +void f5 () +{ + for (int i = 0; i < N; i++) + { + b[i] += a[i]; + if (a[i] < 0) + break; + } +} + +/* +** f6: +** ... +** vcmp.s32 le, q[0-9]+, q[0-9]+ +** vmrs r[0-9]+, p0 @ movhi +** cbnz r[0-9]+, \.L[0-9]+ +** ... +*/ +void f6 () +{ + for (int i = 0; i < N; i++) + { + b[i] += a[i]; + if (a[i] <= 0) + break; + } +} diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp index 02b82e80b4d..769df6cd766 100644 --- a/gcc/testsuite/lib/target-supports.exp +++ b/gcc/testsuite/lib/target-supports.exp @@ -4079,6 +4079,8 @@ proc check_effective_target_vect_early_break { } { expr { [istarget aarch64*-*-*] || [check_effective_target_arm_neon_ok] + || ([check_effective_target_arm_v8_1m_mve_fp_ok] + && [check_effective_target_arm_little_endian]) }}] } # Return 1 if the target supports hardware vectorization of complex additions of